Part Number: AM3517
We have a watchdog, the timeout time is 32.7ms, this watchdog is feed by a 4ms task, a 30s task will read the whole ROM space(about 1Mbytes) to do CRC check, when 30s task read the ROM, cache may be flushed, and 4ms task may be delayed to beyond 32.7ms. 4ms task has higher priority than 30s task.
Our question is what is max number of cache will be flushed in one time, and how much time it will spend?
Our code run on ROM and use SRAM as data ram, ROM and SRAM are both accessed through GPMC bus.
