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AM3354: LCDC byte swap

g.f.
Guru 15520 points

Part Number: AM3354

Hi,

I have a question about AM335x LCDC register.

In TRM(spruhh73o)page.1930 "Table 13-29 LCDDMA_CTRL Register",
there are no vaule written for bit[3] byte_swap.
I guess value '0' will be byte_swap disable and value '1' will be byte_swap enable,
is it correct?

I understand as this byte_swap need to be enabled with "bigendian re-ordering enable"
when processor is operating in big endian mode.
If processor is operating in Little endian mode, I should set this byte_swap to disable, is it correct?

best regards,
g.f.

  • 0
    TI__Guru**** 393215 points
    Hi,

    Table 13-29 states:

    "byte_swap: This bit controls the byte lane ordering of the data on the output of the DMA module. It works in conjunction with the big-endian bit. See the big-endian description for configuration guidelines."

    "bigendian: Big Endian Enable. Use this bit when the processor is operating in Big Endian mode AND writes to the frame buffer(s) are less than 32 bits wide. Only in this scenario do we need to change the byte alignment for data coming into the FIFO from the frame buffer(s).
    0 = Big Endian data reordering disabled.
    1 = Big Endian data reordering enabled."

    AM335x MPU is always operating in Little Endian mode, so these bits have no significance and should be left in their default state.
  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.
    I understood.

    best regards,
    g.f.