• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 100 subscribers
  • Views 585 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA3: Max Clock of MCASP1 AHCLKR on TDA3

JP Park95
Expert 1100 points

Part Number: TDA3

Hi

I need to use 98.304MHz on MCASP1 AHCLKR and ACLKR on TDA3.

According to the figure below, the maximum is 50MHZ.

According to the figure below, the maximum is 100MHZ.

What is the Max Clock of MCASP1 AHCLKR AHCLKR and ACLKR on TDA3 ?

Regards,
JP Park

  • 0
    TI__Expert 4885 points
    Hi, JP Park,

    Please, attach the figures you are referring to.

    Which package and silicon revision do you use?

    Furthermore, see Table 7-x. Timing Requirements for McASP1 in Data Manual to check the maximum frequency.

    Regards,
    Mariya
  • 0 in reply to Mariya Petkova
    TI__Expert 4885 points
    Hi, JP Park,

    Now the figures are visible. I forwarded your question to DM team for more clarification.

    Regards,
    Mariya
  • 0 in reply to Mariya Petkova
    Expert 1100 points
    Hi, Mariya,

    Which package and silicon revision do you use?
    -> TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

    TDA3x DM is TDA3x_ABF_SR2.0_DM_vA.pdf.

    Thank you for your prompt reply.

    Regards,
    JP Park
  • 0 in reply to JP Park95
    TI__Intellectual 1245 points
    Hi, JP Park,

    The maximum allowed frequency for communication with companion device is presented in Timing Requirements and Switching Characteristics.
    In TDA3x case - Maximum allowed frequency for communication over McASP, between SoC and companion device, is 50MHz.

    Maximum Supported Frequency table lists the clock source options for each module on this device, along with the maximum frequency that module can accept. Those clocks are used from the module's integrated clock generators to adjust the required communication clocks.

    Thanks,
    Dian
  • 0 in reply to Dian Iliev
    Expert 1100 points
    Hi Dian

    Thank you for your response.

    Thanks,
    JP Park
  • 0 in reply to JP Park95
    TI__Mastermind 18420 points
    JP Park,
    Please note that we have no AHCLKR pin in this device. 50-MHz restriction however applies also to the ACLKR pin and respective Transmitter pins.
    MCASP clock options are described in the TRM starting from Figure 24-114. McASP Module Block Diagram, and following 3 figures.
    You can see also that clocks can be derived from AUXCLK (up to 192 MHz).
    One way or the other, pins will limit MCASP to 50MHz.

    Regards,
    Stan