RTOS/am5726: Issue with PCIe LLD function on M4

David Beaulieu

Expert 1280 points

Part Number: AM5726
Other Parts Discussed in Thread: AM5726

Tool/software: TI-RTOS

Hi,

This is a follow-up question to this thread:

Now, I have hit another problem.

As suggested in the above thread, I have re-map the PCIe configuration space on the M4 from 0x2000_0000 to 0xA000_0000. Now, if I use the memory browser, I can see the remote device and vendor id at address 0xA400_4000. Now, I tried to used the PCIe LLD to read these registers. I used the following code:

pcieRegisters_t myRegs = {0};

pcieVndDevIdReg_t myRemoteCfgDevAndVendorID = {0};
myRegs.vndDevId = &myRemoteCfgDevAndVendorID;

if ((retVal = Pciev1_readRegs (handle, pcie_LOCATION_REMOTE, &myRegs)) != pcie_RET_OK)
{
  Log_print1(Diags_ERROR, "Read REMOTE DEVICE AND VENDOR ID register failed! retVal=%d\n", retVal);
}
else
{
  Log_print2(Diags_INFO, "Local Vendor ID: %x, Device ID: %x\n", myRemoteCfgDevAndVendorID.vndId, myRemoteCfgDevAndVendorID.devId);
}

My first problem is that I am always getting 0xFFFF for both ID.

The second problem I have is that when I try to force a read at address 0xA400_4000, the M4 crashes and I get the following outputted in the Linux console:

[   45.094907] omap_l3_noc 44000000.ocp: L3 application error: target 5 mod:1 (unclearable)
[   45.094920] omap_l3_noc 44000000.ocp: L3 debug error: target 5 mod:1 (unclearable)

Why can I read it in the memory browser but I can't read the value in the code?

Best regards,

- David

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 David Beaulieu over 8 years ago

Expert 1280 points

Part Number: AM5726

Tool/software: TI-RTOS

Hi,

In my project, I have a AM5726 connected to a Cyclone V FPGA throught PCIe. So far, we have been able to properly enumerate the PCIe endpoint in the DSP as well as configure the DMA transactions between the FPGA and DSP. However, we need the MIPS used by the PCIe driver in the DSP for codec processing. So, we decided to move PCIe driver in the M4

I am struggling to get the PCIe enumeration to properly work in the M4 processor. I have another thread already for that problem.

I was wondering if the following workflow could be implemented to work around my problem.

Enumerate the PCIe endpoint on the DSP
Configure the OB and IB translation in the DSP. However, use L2SRAM address from the M4 core 0.
Configure the DMA in the DSP
Configure the PCIe interrupt to be processed by the M4.

Is that feasible in the Sitara processor?

Thanks,

- David

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Moving this to the original thread.

0 David Beaulieu over 8 years ago in reply to Biser Gatchev-XID

Expert 1280 points

Hi,

I haven't heard anything from TI on this.
Does anyone has any ideas why this exception is being generated on the ARM?

Regards,
- David

0 lding over 8 years ago in reply to David Beaulieu

TI__Guru* 95265 points

David,

Sorry for the late response! For why M4 can see the PCIE DeviceID/Vendor ID from CCS menory Window but not from code, I will try our setup tomorrow with code running on M4.

For why Linux force read crash, how do you read 0xa000_4000 from M4? Is it something like devmem2? Or you have an application send/receive IPC messge between Linux and M4?

For the proposal,
1.Enumerate the PCIe end point on the DSP
2.Configure the OB and IB translation in the DSP. However, use L2SRAM address from the M4 core 0.
3.Configure the DMA in the DSP
4.Configure the PCIe interrupt to be processed by the M4.

Points 1 and 2 are one time work. You can do it with DSP code. From TRM, M4 can also access L2SRAM 0x4100_0000.

Point 3, configuring EDMA is one-time, what about the next transfer? Do you reload the same EDMA OPT parameter or you have to use some different parameters (e.g. source, destination) each time and have to re-configure by DSP? If this is repeated work, have you consider using M4 for EDMA?

Point 4, it is also possible.

My overall thinking is the coding complexity to split the PCIE initalization, EDMA, interrupt over several places.

Regards, Eric

0 David Beaulieu over 8 years ago in reply to lding

Expert 1280 points

Hi Eric,

No apologies required. But this just became something important on the project I am working on and I don't want this to become the critical path :).

On the M4, I am reading 0xA000_4000 using the PCIe LLD read register function in the M4 processor running SYS/BIOS. I also tried de-referencing a pointer to 0xA000_4000 and got the same result. Everytime I try to read a value from the PCIe remote configuration registers, I get the L3 error printed on the Linux console. Afterwards, the M4 processor becomes unresponsive.

Now, like you pointed out, I am trying to limit the complexity of the application. I would like to have everything in the M4 if possible (PCIe configuration and enumeration, EDMA setup and PCIe interrupt processing).

With regards to EDMA, I have a ping-pong buffer so my param set can be program at initialization phase. No reconfiguration required between transfer since I have set the linkAddr parameter in the param set as well. The EDMA transfer needs to be started upon reception of the PCIe interrupt.

Again, thanks for your help. Any help would be greatly appreciated.
Regards,
- David

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RTOS/am5726: Issue with PCIe LLD function on M4