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AM3352: MDIO_DATA timing question

Nico
Expert 6160 points

Part Number: AM3352

Hi,

looking at figure 7-5 of datasheet , MDIO seems synced based on MDIO_CLK (MDC) positive edge synchronisation.

when measuring this : it rather looks like it is synced based on MDC negative edge sync ... (see below picture)

can you clarify is this is a datasheet mistake or a bad understanding on my side.

Thanks 

  • 0
    TI__Guru**** 393215 points
    Hi,

    There are two diagrams in the datasheet - MDIO_DATA Timing - Input Mode and MDIO_DATA Timing - Output Mode. What are you measuring?
  • 0
    TI__Guru* 85085 points
    Nico
    From internal discussions I confirm that this appears to be a datasheet issue.
    How is this impacting your customer?
  • 0 in reply to Mukul Bhatnagar
    TI__Expert 6160 points

    Hi , there is no impact at customer level but only clarification to ensure the components in front will be "compatible" .

    As the TI AM335x CPSW & MDIO works well will all Eth PHY , taht's the principal and we wanted to ensure it was a datasheet mistake.

    thanks

    Nicolas

  • 0 in reply to Nico
    TI__Guru 63605 points

    The data sheet currently shows MDIO_DATA changing on the rising edge of MDIO_CLK. However, MDIO_DATA actually changes on the falling edge of MDIO_CLK.

    The “MDIO_DATA Timing – Output Mode” figure needs to be updated to show MDIO_DATA changing on the falling edge of MDIO_CLK. This update also requires the “Delay time, MDC high to MDIO valid parameter” values in the “Switching Characteristics for MDIO_DATA” table to be updated where the new minimum value is -10ns and the new maximum value is 10ns.

     In summary, MDIO_DATA may change anytime between 10ns before the falling edge of MDIO_CLK and 10ns after the falling edge of MDIO_CLK.

    Regards,
    Paul