PCIE interface about C6674

Sunny

Hi TI professors,

I want to design a based on C6674 and FPGA digital signal platform. Now I want to make DSP connect FPGA by PCIE. I don't konw if DSP can directly connect with FPGA？What are the input and output levels of the PCIE interface of the DSP? Thank u!

over 8 years ago

0 Victor Kazmirenko over 8 years ago

Guru 13202 points

Hi!

When it comes to hardware design, I would recommend Hardware Design Guide for KeyStone I Devices Application Report SPRABI2, then you may trace down to SerDes Implementation Guide for KeyStone I Devices Application Report. They state:

All SerDes-based interfaces should be AC-coupled. As long as the SerDes link partner uses CML logic, the AC-coupling capacitor is the only external termination required.

To assure you, in our design for C6670 and Spartan 6 we place only capacitors on the way between DSP's and FPGA's pins. Another valuable resource is EVM reference design. Grab those files at Advantech and work through.

Before you head in, I would suggest to skim through bunch of PCIe related question on the forum, here is my experience https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/444356.

SerDes Implementation Guide for

KeyStone I Devices Application Report

Processors

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PCIE interface about C6674