Hi,
I using OMAP 3530 on Mistral Board and I'm having problems in run SDMA interrupt correct on IVA2 subsystem.
I configure de SDMA module and it is working correctly in CCS4.
I configure DMA4_CICR and I see that DMA4_CSR is set. I also configure DMA4_IRQENABLE (line 0) to be set on logic channel bit. I see that SDMA interrupt line 0 and line 1 is shared between IVA2 subsystem.
But I didn't see the event set (EVTFLAG) on IVA2. The following code
// Clear All Interrupts
*( &SDMA_BASE + DMA4_CSR + uiOffset) = 0x00001FFE;
// Enable End Of Frame Interrupt
*( &SDMA_BASE + DMA4_CICR + uiOffset) = 0x00000008;
// Enable DMA Mask Bit To Work
*( &SDMA_BASE + DMA4_IRQENABLE) |= 0x00000001 << uiDMAChannel;
OBS.: uiDMAChannel is zero (logic channel) and uiOffset is the offset address of SDMA (also zero in this case).
I notice that in Section 1.6.1.2 (SDMA Technical Reference Manual) in Table 1-9 is said:
DMA4_IRQENABLE_L1 - 0x4805601c (ADDR) - 0x00022800 (VALUE) - Interrupts of channels 11, 12, and 13 are unmasked on IRQ line L1.
This is correct ? Should the VALUE be 0x00003800 ?
Anyone can tell me what is the problem ? Or something I should study ?
Thanks.
