Linux/DRA756: 4ch display on Jacinto6 and PSDKLA

yangwoo Lee

Intellectual 910 points

Part Number: DRA756

Tool/software: Linux

Hello I'm working on Jacinto6 with PSDKLA 3.02.4ch-disp.log

My custom board have 4display(hdmi, ser-disp0, ser-disp1, ser-disp2)

I changed dra7-evm.dts for my 4ch display. but there are error when I enable 4 display in dtb.

When I try it with hdmi, disp0, disp2(without disp1) , It was work

but both of case hdmi, disp0, disp1 and hdmi, disp0, disp1, disp2 was not work.

* I attached the log message with enable DSS debug

please check my dts

/ {
lcd_fpd1: display_fpd1 {
  /*
  * This is not really a dpi panel, but panel-dpi driver
  * works as dummy panel driver.
  */
  compatible = "lg,lp101wx2", "panel-dpi";
  //label = "lcd_fpd1";
  //enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
  status = "okay";

  panel-timing {
   clock-frequency = <64000000>;
   hactive = <1280>;
   vactive = <720>;

   hfront-porch = <48>;
   hback-porch = <80>;
   hsync-len = <32>;

   vfront-porch = <3>;
   vback-porch = <13>;
   vsync-len = <5>;

   hsync-active = <0>;
   vsync-active = <0>;
   de-active = <1>;
   pixelclk-active = <0>;
  };

  port@lcd1 {
   fpd_in1: endpoint {
    remote-endpoint = <&dpi_out1>;
   };
  };
};
};

/ {
lcd_fpd2: display_fpd2 {
  /*
  * This is not really a dpi panel, but panel-dpi driver
  * works as dummy panel driver.
  */
  compatible = "lg,lp101wx2", "panel-dpi";
  //label = "lcd_fpd2";
  //enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
  status = "okay";

  panel-timing {
   clock-frequency = <64000000>;
   hactive = <1280>;
   vactive = <720>;

   hfront-porch = <48>;
   hback-porch = <80>;
   hsync-len = <32>;

   vfront-porch = <3>;
   vback-porch = <13>;
   vsync-len = <5>;

   hsync-active = <0>;
   vsync-active = <0>;
   de-active = <1>;
   pixelclk-active = <0>;
  };

  port@lcd2 {
   fpd_in2: endpoint {
    remote-endpoint = <&dpi_out2>;
   };
  };
};
};

/ {
lcd_fpd3: display_fpd3 {
  /*
  * This is not really a dpi panel, but panel-dpi driver
  * works as dummy panel driver.
  */
  compatible = "lg,lp101wx2", "panel-dpi";
  //label = "lcd_fpd3";
  //enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
  status = "okay";

  panel-timing {
   clock-frequency = <64000000>;
   hactive = <1280>;
   vactive = <720>;

   hfront-porch = <48>;
   hback-porch = <80>;
   hsync-len = <32>;

   vfront-porch = <3>;
   vback-porch = <13>;
   vsync-len = <5>;

   hsync-active = <0>;
   vsync-active = <0>;
   de-active = <1>;
   pixelclk-active = <0>;
  };

  port@lcd3 {
   fpd_in3: endpoint {
    remote-endpoint = <&dpi_out3>;
   };
  };
};
};

&dss {
status = "okay";

vdda_video-supply = <&ldoln_reg>;
pinctrl-names = "default";
pinctrl-0 = <&vout1_pins &vout2_pins &vout3_pins>;

ports {
  #address-cells = <1>;
  #size-cells = <0>;
  status = "okay";

  port@lcd1 {
   reg = <0>;
   status = "okay";
   dpi_out1: endpoint {
    remote-endpoint = <&fpd_in1>;
    data-lines = <24>;
   };
  };

  port@lcd2 {
   reg = <1>;
   status = "okay";
   dpi_out2: endpoint {
    remote-endpoint = <&fpd_in2>;
    data-lines = <24>;
   };
  };

  port@lcd3 {
   reg = <2>;
   status = "okay";
   dpi_out3: endpoint {
    remote-endpoint = <&fpd_in3>;
    data-lines = <24>;
   };
  };
};
};

over 8 years ago

0 Yordan Kamenov over 8 years ago

TI__Mastermind 42515 points

Hi Yangwoo,

I have forwarded your question to DSS expert.

Regards,
Yoradn

0 yangwoo Lee over 8 years ago in reply to Yordan Kamenov

Intellectual 910 points

Thank you Yordan.

Incidentally, in my kernel log, first dump_stack call is come from " WARN_ON(omap_crtc->vblank_irq.registered)" of omap_crtc_atomic_flush of omap_crtc.c

This situation is generated with enabling disp0, disp1.(I tried only disp0, but it was ok. and I also tried disp0 and disp2, it was also ok)

It looks that disp0 and disp1 have some conflict about irq.

I'm using 4 as number of CRTC

0 Venkat Mandela over 8 years ago in reply to yangwoo Lee

TI__Expert 5960 points

Hi,

Lets start with the simpler case disp0 + disp1. Can you please run the below script and send me the logs?

git.ti.com/.../dss_clockdumps.sh

I want to check if the clock configuration is right before moving to irq configuration.

regards,
Venkat

0 yangwoo Lee over 8 years ago in reply to Venkat Mandela

Intellectual 910 points

Hello

Attachment is log for disp0,disp1

There are some my dummy log.. about omap_irq_register like "Before ######### ywdbg:omap_irq_register:72: 1"

Please understand about it because my yocto build has problem, I can't get clean log now.

When booting, there was no error log but disp0 is not work, but when I excute kmscube or weston, it generate error, so I excute kmscube end of boot

disp0disp1.log

0 yangwoo Lee over 8 years ago in reply to Venkat Mandela

Intellectual 910 points

Sorry I missed your script
Below is result

root@dra7xx-evm:~# ./debug_dss_clockdumps.sh

=====================DSS clock script===================
Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x00000286
video1 PLL : Enabled
video2 PLL : Disabled
HDMI PLL : Disabled
DSI1_A_CLK mux : DPLL Video1
DSI1_B_CLK mux : DPLL Video1
DSI1_C_CLK mux : DPLL Video1

DSS_CTRL (0x58000040) = 0x00011001
2: LCD1 clk switch : DSI1_A_CLK
3: LCD2 clk switch : DSI1_B_CLK
10: LCD3 clk switch : DSS clk
1: func clk switch : DSS clk
13: DPI1 output : LCD1

DSS_STATUS (0x5800005C) = 0x01409282

DSI_CLK_CTRL (0x58004054) = 0x80004001

========================================================
Register dump for DPLL video1
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58004300 | 0x00000018 |
| 0x58004304 | 0x00002283 |
| 0x58004308 | 0x00000000 |
| 0x5800430C | 0x01AE004E |
| 0x58004310 | 0x00616008 |
| 0x58004314 | 0x00000000 |
| 0x58004318 | 0x00000000 |
| 0x5800431C | 0x00000000 |
| 0x58004320 | 0x00000000 |
|----------------------------|
Details for DPLL video1
PLL status : Locked
M4 hsdiv(1) : Active
M5 hsdiv(2) : inactive
M6 hsdiv(3) : inactive
M7 hsdiv(4) : inactive

PLL_REGM = 1792
PLL_REGN = 39
M4 DIV = 13
M6 DIV = 0
M7 DIV = 0

Clock calculations (DPLL video1)
sysclk = 20000000
DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1792000000
M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 128000000
M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 0
M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0

========================================================
Clock O/P of MUXes
DSI1_A_CLK : 128000000
DSI1_B_CLK : 0
DSI1_C_CLK : 0

2: LCD1 clk : 128000000
3: LCD2 clk : 0
10: LCD3 clk : 192000000
1: func clk : 192000000

LCD1 logic clk(/ 1 ) : 128000000 pix clk(/ 2 ) : 64000000
LCD2 logic clk(/ 1 ) : 0 pix clk(/ 2 ) : 0
LCD3 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 48000000

root@dra7xx-evm:~#

0 yangwoo Lee over 8 years ago in reply to yangwoo Lee

Intellectual 910 points

Sorry above result is not correct.
I tested again with cleaned kernel
Please check this log.

dra7xx-evm login: root
root@dra7xx-evm:~# ls
debug_dss_clockdumps.sh utils
root@dra7xx-evm:~# ./debug_dss_clockdumps.sh

=====================DSS clock script===================
Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x00000200
video1 PLL : Enabled
video2 PLL : Enabled
HDMI PLL : Enabled
DSI1_A_CLK mux : DPLL Video1
DSI1_B_CLK mux : DPLL Video1
DSI1_C_CLK mux : DPLL Video2

DSS_CTRL (0x58000040) = 0x00091001
2: LCD1 clk switch : DSI1_A_CLK
3: LCD2 clk switch : DSI1_B_CLK
10: LCD3 clk switch : DSI1_C_CLK
1: func clk switch : DSS clk
13: DPI1 output : LCD1

DSS_STATUS (0x5800005C) = 0x02409282

DSI_CLK_CTRL (0x58004054) = 0x80004001

========================================================
Register dump for DPLL video1
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58004300 | 0x00000018 |
| 0x58004304 | 0x00002603 |
| 0x58004308 | 0x00000000 |
| 0x5800430C | 0x000E004E |
| 0x58004310 | 0x00E06008 |
| 0x58004314 | 0x0000000D |
| 0x58004318 | 0x00000000 |
| 0x5800431C | 0x00000000 |
| 0x58004320 | 0x00000000 |
|----------------------------|
Details for DPLL video1
PLL status : Locked
M4 hsdiv(1) : inactive
M5 hsdiv(2) : inactive
M6 hsdiv(3) : Active
M7 hsdiv(4) : inactive

PLL_REGM = 1792
PLL_REGN = 39
M4 DIV = 0
M6 DIV = 13
M7 DIV = 0

Clock calculations (DPLL video1)
sysclk = 20000000
DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1792000000
M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 0
M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 128000000
M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0

========================================================
Register dump for DPLL video2
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58009300 | 0x00000018 |
| 0x58009304 | 0x00002283 |
| 0x58009308 | 0x00000000 |
| 0x5800930C | 0x01AE004E |
| 0x58009310 | 0x00616008 |
| 0x58009314 | 0x00000000 |
| 0x58009318 | 0x00000000 |
| 0x5800931C | 0x00000000 |
| 0x58009320 | 0x00000000 |
|----------------------------|
Details for DPLL video2
PLL status : Locked
M4 hsdiv(1) : Active
M5 hsdiv(2) : inactive
M6 hsdiv(3) : inactive
M7 hsdiv(4) : inactive

PLL_REGM = 1792
PLL_REGN = 39
M4 DIV = 13
M6 DIV = 0
M7 DIV = 0

Clock calculations (DPLL video2)
sysclk = 20000000
DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1792000000
M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 128000000
M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 0
M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0

========================================================
Register dump for DPLL hdmi
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58040200 | 0x00000018 |
| 0x58040204 | 0x00000003 |
| 0x58040208 | 0x00000000 |
| 0x5804020C | 0x00037C0E |
| 0x58040210 | 0x00602004 |
| 0x58040214 | 0x00001400 |
| 0x58040218 | 0x00000000 |
| 0x5804021C | 0x00000000 |
| 0x58040220 | 0x00069374 |
|----------------------------|
Details for DPLL hdmi
PLL status : Locked
M4 hsdiv(1) : inactive
M5 hsdiv(2) : inactive
M6 hsdiv(3) : inactive
M7 hsdiv(4) : inactive

PLL_REGM = 446
PLL_REGN = 7
M4 DIV = 0
M6 DIV = 0
M7 DIV = 0
PLL_REGM2 = 1
PLL_REGM_F = 1

Clock calculations (DPLL hdmi)
sysclk = 20000000
CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 1115000000

========================================================
Clock O/P of MUXes
DSI1_A_CLK : 0
DSI1_B_CLK : 128000000
DSI1_C_CLK : 128000000

2: LCD1 clk : 0
3: LCD2 clk : 128000000
10: LCD3 clk : 128000000
1: func clk : 192000000

LCD1 logic clk(/ 1 ) : 0 pix clk(/ 2 ) : 0
LCD2 logic clk(/ 1 ) : 128000000 pix clk(/ 2 ) : 64000000
LCD3 logic clk(/ 1 ) : 128000000 pix clk(/ 2 ) : 64000000

root@dra7xx-evm:~#

0 yangwoo Lee over 8 years ago in reply to Venkat Mandela

Intellectual 910 points

Hi Venkat.

Fullscreen 0001-HACK-dss-fix-to-enable-4channel-display.patch.log Download

From 753888ad7e275d0bb657a46fb3e7a47e6edaaa24 Mon Sep 17 00:00:00 2001
From: yangwoo <yangwoo.lee@hyundai-autron.com>
Date: Fri, 24 Mar 2017 14:44:14 +0900
Subject: [PATCH] HACK: dss: fix to enable 4channel display

---
 drivers/gpu/drm/omapdrm/dss/dpi.c | 9 +++++++--
 drivers/gpu/drm/omapdrm/dss/pll.c | 6 ++++--
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c
index a5209c9..b5ba322 100644
--- a/drivers/gpu/drm/omapdrm/dss/dpi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dpi.c
@@ -197,8 +197,13 @@ static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
 {
 	struct dpi_clk_calc_ctx *ctx = data;
 
-	ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc;
-	ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;
+//	ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc;
+//	ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;
+
+	ctx->pll_cinfo.mX[0] = m_dispc;
+	ctx->pll_cinfo.clkout[0] = dispc;
+	ctx->pll_cinfo.mX[2] = m_dispc;
+	ctx->pll_cinfo.clkout[2] = dispc;
 
 	return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
 			dpi_calc_dispc_cb, ctx);
diff --git a/drivers/gpu/drm/omapdrm/dss/pll.c b/drivers/gpu/drm/omapdrm/dss/pll.c
index 65c478d..e1f683d 100644
--- a/drivers/gpu/drm/omapdrm/dss/pll.c
+++ b/drivers/gpu/drm/omapdrm/dss/pll.c
@@ -438,10 +438,12 @@ int dss_pll_write_config_type_a(struct dss_pll *pll,
 
 	l = readl_relaxed(base + PLL_CONFIGURATION2);
 	l = FLD_MOD(l, 1, 14, 14);			/* PHY_CLKINEN */
-	l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16);	/* M4_CLOCK_EN */
+//	l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16);	/* M4_CLOCK_EN */
+	l = FLD_MOD(l, 1, 16, 16);	/* M4_CLOCK_EN */
 	l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18);	/* M5_CLOCK_EN */
 	l = FLD_MOD(l, 0, 20, 20);			/* HSDIVBYPASS */
-	l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23);	/* M6_CLOCK_EN */
+//	l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23);	/* M6_CLOCK_EN */
+	l = FLD_MOD(l, 1, 23, 23);	/* M6_CLOCK_EN */
 	l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25);	/* M7_CLOCK_EN */
 	writel_relaxed(l, base + PLL_CONFIGURATION2);
 
-- 
1.9.1

I can see 4ch display now with my HACK code(enable clock with hard coding).

Please check attached patch.

But still I don't know that result is correct or not. And I need correct way to enable it.

Please verify my result if it is correct or not.

And please give me patch for enable it as correct way(not hard coding way)

=====================DSS clock script===================

Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x00000200

video1 PLL : Enabled

video2 PLL : Enabled

HDMI PLL : Enabled

DSI1_A_CLK mux : DPLL Video1

DSI1_B_CLK mux : DPLL Video1

DSI1_C_CLK mux : DPLL Video2

DSS_CTRL (0x58000040) = 0x00091001

2: LCD1 clk switch : DSI1_A_CLK

3: LCD2 clk switch : DSI1_B_CLK

10: LCD3 clk switch : DSI1_C_CLK

1: func clk switch : DSS clk

13: DPI1 output : LCD1

DSS_STATUS (0x5800005C) = 0x02409282

DSI_CLK_CTRL (0x58004054) = 0x80004001

========================================================

|----------------------------|

| Address (hex) | Data (hex) |

|----------------------------|

| 0x58004300 | 0x00000018 |

| 0x58004304 | 0x00002683 |

| 0x58004308 | 0x00000000 |

| 0x5800430C | 0x01AE004E |

| 0x58004310 | 0x00E16008 |

| 0x58004314 | 0x0000000D |

| 0x58004318 | 0x00000000 |

| 0x5800431C | 0x00000000 |

| 0x58004320 | 0x00000000 |

|----------------------------|

Details for DPLL video1

PLL status : Locked

M4 hsdiv(1) : Active

M5 hsdiv(2) : inactive

M6 hsdiv(3) : Active

M7 hsdiv(4) : inactive

PLL_REGM = 1792

PLL_REGN = 39

M4 DIV = 13

M6 DIV = 13

M7 DIV = 0

Clock calculations (DPLL video1)

sysclk = 20000000

DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1792000000

M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 128000000

M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 128000000

M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0

========================================================

|----------------------------|

| Address (hex) | Data (hex) |

|----------------------------|

| 0x58009300 | 0x00000018 |

| 0x58009304 | 0x00002683 |

| 0x58009308 | 0x00000000 |

| 0x5800930C | 0x01AE004E |

| 0x58009310 | 0x00E16008 |

| 0x58009314 | 0x0000000D |

| 0x58009318 | 0x00000000 |

| 0x5800931C | 0x00000000 |

| 0x58009320 | 0x00000000 |

|----------------------------|

Details for DPLL video2

PLL status : Locked

M4 hsdiv(1) : Active

M5 hsdiv(2) : inactive

M6 hsdiv(3) : Active

M7 hsdiv(4) : inactive

PLL_REGM = 1792

PLL_REGN = 39

M4 DIV = 13

M6 DIV = 13

M7 DIV = 0

Clock calculations (DPLL video2)

sysclk = 20000000

DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1792000000

M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 128000000

M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 128000000

M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0

========================================================

|----------------------------|

| Address (hex) | Data (hex) |

|----------------------------|

| 0x58040200 | 0x00000018 |

| 0x58040204 | 0x00000003 |

| 0x58040208 | 0x00000000 |

| 0x5804020C | 0x00037C0E |

| 0x58040210 | 0x00602004 |

| 0x58040214 | 0x00001400 |

| 0x58040218 | 0x00000000 |

| 0x5804021C | 0x00000000 |

| 0x58040220 | 0x00069374 |

|----------------------------|

Details for DPLL hdmi

PLL status : Locked

M4 hsdiv(1) : inactive

M5 hsdiv(2) : inactive

M6 hsdiv(3) : inactive

M7 hsdiv(4) : inactive

PLL_REGM = 446

PLL_REGN = 7

M4 DIV = 0

M6 DIV = 0

M7 DIV = 0

PLL_REGM2 = 1

PLL_REGM_F = 1

Clock calculations (DPLL hdmi)

sysclk = 20000000

CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 1115000000

========================================================

Clock O/P of MUXes

DSI1_A_CLK : 128000000

DSI1_B_CLK : 128000000

DSI1_C_CLK : 128000000

2: LCD1 clk : 128000000

3: LCD2 clk : 128000000

10: LCD3 clk : 128000000

1: func clk : 192000000

LCD1 logic clk(/ 1 ) : 128000000 pix clk(/ 2 ) : 64000000

LCD2 logic clk(/ 1 ) : 128000000 pix clk(/ 2 ) : 64000000

LCD3 logic clk(/ 1 ) : 128000000 pix clk(/ 2 ) : 64000000

regards,

yangwoo

0 Venkat Mandela over 8 years ago in reply to yangwoo Lee

TI__Expert 5960 points

Hi,

I see that you are enabling both M4 and M6 dividers for the VideoPLL irrespective of which divider is used. This should be OK as a temporary workaround. I will check internally on how this can be enabled cleanly. Please note that this could take some time.

regards,
Venkat

0 yangwoo Lee over 8 years ago in reply to Venkat Mandela

Intellectual 910 points

Thank you for confirm it.
I will use it until made it cleanly by TI, if there is no issue.

Processors

Processors forum

Linux/DRA756: 4ch display on Jacinto6 and PSDKLA