Tool/software: Linux
We have a sitara design using 1 DDR3 memory chip from Hynix. (H5TQ2G63DFR-H9C).
The DDR3 clock is set to 303MHz.
Kernel 3.2.0
Now we wanted to change the DDR memory to 4Gbit device (H5TQ4G63CFR-RDC).
Comparing both memory datasheets does not show any timing diff's, so the same clock freq. should be applicable for the 4Gbit device.
But we had to bring back the clock freq. to 285 MHz in the U-boot config registers in order to properly boot. This is however not the frequency we would like to continue with. We do not want to lower the frequency. The issue might indicate we are facing a possible timing violation in the first place.
See below the details of the register values we are currently using. The setting for the Micron MT41J128M16JT-125 is used. (Although we use a Hynix device).
CM_CLKSEL_DPLL_DDR Register (offset = 40h) : 0x00012F17
CM_DIV_M2_DPLL_DDR Register (offset = A0h) : 0x00000201
SDRAM_CONFIG (0x4c000008) : 0x61C04AB2
SDRAM_CONFIG2 (0x4c00000C) : 0x00000000
SDRAM_REF_CTRL (0x4c000010) : 0x0000093B
u-boot i (ddr_defs.h) :
/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
/* Micron MT41J128M16JT-125 */
#define DDR3_EMIF_READ_LATENCY 0x100006 /* Enable Dynamic Power Down */
#define DDR3_EMIF_TIM1 0x0888A39B
#define DDR3_EMIF_TIM2 0x26337FDA
#define DDR3_EMIF_TIM3 0x501F830F
#define DDR3_EMIF_SDCFG 0x61C04AB2
#define DDR3_EMIF_SDREF 0x0000093B
#define DDR3_ZQ_CFG 0x50074BE4
#define DDR3_DLL_LOCK_DIFF 0x1
#define DDR3_RATIO 0x40
#define DDR3_INVERT_CLKOUT 0x1
#define DDR3_RD_DQS 0x3B
#define DDR3_WR_DQS 0x85
#define DDR3_PHY_WR_DATA 0xC1
#define DDR3_PHY_FIFO_WE 0x100
#define DDR3_IOCTRL_VALUE 0x18B
