TMS320C6678: Issue with accessing NVSRAM using SPI

Hi Noufal,

I've forwarded this to the hardware experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

Hi Noufal,
Could you provide some additional information on the behavior that you are observing? You stated that you are able to send data but not read data. Does the data appear on the SO line when you attempt to read the memory? If data is present, are you seeing any of the data appear in the internal buffer in the SPI portion of the c6678?
Regards,
Bill

hi sir, 

we are not observing any data on SO line.

we tried to read status register. we are sending command as follows,

1. send WR_EN command --- we can see this data going through SI line.

2. send command for reading status register --  we can see this data going through SI line.

3.then read back RX buffer, but we didnt get any value. expected value was 0x02, but we got 0x00 always.

we also observed that for sending first two commands, we are seeing 8 clock pulses for each command on SCK line. after that no clock has seen. But for receiving we need 8 more clock pulses (total of 24 pulses).

we tried with holdong CS line for 24 pulses. but we observed only 16 pulses.

Hi Noufal,

This doesn't sound like a hardware issue but a configuration issue for the SPI in the C6678. I'm going to contact the software support team and point them at your question but let me make a couple of suggestions.

1) The memory that you are using operates in the same manner as the SPI memory on the C6678 EVM. Have you compared your code with the code delivered with the EVM?

2) I think you are missing a step in the sequence you have shown above.  

• Issue the WR_EN command with the CSHOLD bit =0. This should set the CS low, clock out the command and set the CS high.
• Issue the Read status command with the CSHOLD bit=1. This should set the CS low, clock out the 8 bits of the command. The CS should remain low afterwards.
• Issue a dummy 8 bit write with the CSHOLD bit=0. This should clock eight bits on the data out line which the memory will ignore. If the memory has recieved the read status command correctly, it will drive the status bits out with each of the clock pulses. CS will go high at the end of the access.
• Read the receive buffer to get the status. 

Let me know if that changes the behavior. 

Regards,

Bill

Sir,

"Issue the Read status command with the CSHOLD bit=1. This should set the CS low, clock out the 8 bits of the command. The CS should remain low afterwards."
for making CS low, we should set the CSHOLD bit =0, right? as u told in the point-1.

please clarify the point again..

Hi sir,

one more doubt,

"1.The memory that you are using operates in the same manner as the SPI memory on the C6678 EVM. Have you compared your code with the code delivered with the EVM?"

can u please tell me the path where example code is given???

Hi sir,

we need clarifications on below points.
1. NVSRAM chip requires 40bits of data to be sent in a single SPI transaction from c6678 for read/write. As per "SPRUGP2A", max char length is 16 bits. So how can this c6678's SPI controller communicate with NVSRAM ?
2. How the SCLK is controlled from DSP?
a. For reading status register of NVSRAM with WR_EN bit set, we have to pass first WR_EN opcode and followed by read status register opcode. So totally we need 24 clock pulses (8 for WR_EN opcode and 16 for reading status register). But when observed we were able to see only 16 SCLK pulses. So for receiving the status register content, we are not observing any more 8 SCLK pulses.

Please help us regarding the above issues.

PS : Please find the NVSRAM datasheet @ www.cypress.com/.../download .

Hi Sir,

We have following queries
1. Can c6678 communicate with nvsram for read/write, as c6678 SPI has max character length of 16 and we need 48 bits of data to be sent to nvsram for a single write operation [ 8-> WE_EN opcode + 8 -> write opcode + 24 -> Address + 8-> Data ].
2. How SCLK is controlled in SPI controller of c6678.
a. For reading status register, we have to send WE_EN opcode + read status register opcode + dummy write data, so we need continous 24 SCLK pulses. But while probing we are seeing only 16 SCLK pulses. Then how to get 24 continous clock pulses from c6678.
3. We are refering doc. "sprugp2a".

PS : Please find the link for nvsram datasheet www.cypress.com/.../download

Hi Noufal,
I've contacted the software support team for additional help on this one but let me add some points about the operation of the SPI.
1) The length of a transfer can be varied up to 16bits and the CSHOLD allows a transfer to end with the CS remaining low. To support a transfer that is longer then 16 bits, you will have to break the transfer into groups of 16 or less and set the CSHOLD between the groups so the CS does not go high between accesses.
2) The read shift register is always clocked whenever SCLK toggles. To create the clocks that will capture the read values you must perform a write. Writing the read opcode to the memory will direct it to drive a value onto the data in line and writing the 8 bit dummy value to create the clocks needed for the memory to drive to read value on to the data in line.
Regards,
Bill