CCS/TMS320C6678: some issues about port re-initialization

Yoonsun Kim

Expert 1870 points

Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hello,

The SRIO configuration between FPGA and c6678 is below.

-. x2 mode: land 0 & lane 1 are connected as one port.

-. direct IO: FPGA sends data to DDR3 memory

-. I can check SRIO status on FPGA: clock_lock, port_initialized, link_initialized, mode_1x, port_error

mode_1x means than the port is initialized with one lane not two lane

1> Port is sometimes initialized as mode_1x not mode_2x.

I need to re-start link negotiation when port is mode_1x.

Is there any control register to start negotiation manually?

And which register can I know if link is initialized 2x mode or 1x mode

2> Reading SP0_ERR_STAT

I made simple function to read SP0_ERR_STAT as below.

Sometime the return value is '0' it means hSrio is NULL. Which case srio handle can be NULL?

uint32_t srio_error_status()
{
    CSL_SrioHandle hSrio;

    hSrio = CSL_SRIO_Open (0);
    if (hSrio == NULL)
        return 0;

    return hSrio->RIO_SP[0].RIO_SP_ERR_STAT;
}

over 9 years ago

0 Cvetolin Shulev-XID over 9 years ago

TI__Guru 65405 points

Hi Yoonsun,

I've forwarded this to the SRIO experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

0 Garrett Ding over 9 years ago in reply to Cvetolin Shulev-XID

TI__Mastermind 43296 points

Yoonsun,

Have you checked PLM Port(n) Path Control Register (PLM_SP(n)_PATH_CTL) to insure PATH MODE is set to mode 2 or mode 3?

It's not possible that srio handler is NULL with instance number 0, see below CSL_SRIO_Open() definition. Instead, RIO_SP_ERR_STAT returns zero.

CSL_SrioHandle CSL_SRIO_Open (Int32 instNum)
{
CSL_SrioHandle ret_val = (CSL_SrioHandle)0;
if (instNum == 0)
{
ret_val = (CSL_SrioHandle)CSL_SRIO_CONFIG_REGS;
}
/* Control comes here implies that an invalid instance number was passed */
return(ret_val);
}

Regards,
Garrett

0 Yoonsun Kim over 9 years ago in reply to Garrett Ding

Expert 1870 points

Garrett,

According to datasheet, bit 0(Port Uninitialized) and bit 1(Port OK) of SP_ERR_STAT are mutually exclusive. Is it possible that RIO_SP_ERR_STAT returns zero?

However, how can I force physical layer to reinitialize the link when I need to re-start SRIO link setup.

0 Garrett Ding over 9 years ago in reply to Yoonsun Kim

TI__Mastermind 43296 points

Yoonsun,

It's interesting - bit 0 and bit 1 should be mutually exclusive. Did you step into the function CSL_SRIO_Open() to pinpoint the return value?

The sequence described for keystone software assisted error recovery https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/491162 should help reinitialize the link as well.

Regards,
Garrett

0 Yoonsun Kim over 9 years ago in reply to Garrett Ding

Expert 1870 points

Garrett,

I modified srio_error_status function. The function returns only SP_ERR_STAT.

Anyway, it returns sometimes '0'.

Can you give me any clue which case SP_ERR_STAT is '0'?

uint32_t srio_error_status(void)
{
	CSL_SrioHandle hSrio;

    hSrio = CSL_SRIO_Open (0);
//    if (hSrio == NULL)
//        return 0;

    return hSrio->RIO_SP[0].RIO_SP_ERR_STAT;
}

0 Garrett Ding over 9 years ago in reply to Yoonsun Kim

TI__Mastermind 43296 points

Yoonsun,

The register SPn_ERR_STAT self should have bit and bit 1 mutually exclusive, and not be zero, did you check if any chance the memory
hSrio->RIO_SP[0].RIO_SP_ERR_STAT is overwritten?

Regards,
Garrett

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CCS/TMS320C6678: some issues about port re-initialization