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Linux/AM5728: Dynamically loadable PCIe driver

Brad Caldwell
Genius 12595 points

Part Number: AM5728
Other Parts Discussed in Thread: XIO2001

Tool/software: Linux

We have a custom AM572x board with a daughter card connected to the AM572x via PCIe

We plan to power-up our PCIe card after processor boots-up. But looks like AM572x kernel has got a native PCIe driver which goes and probe the device during boot time only.

We are looking for a loadable PCIe kernel module which can be inserted later on after our card is powered ON. Is there a loadable kernel module for PCIe  available?

  • 0
    TI__Guru**** 393215 points
    The software team have been notified. They will respond here.
  • 0 in reply to Rex Chang
    TI__Guru 50170 points
    Hi, Brad,

    The PCIe card itself has a kernel driver which can be a loadable module if that is what you want. This module can be activated through modprobe command after the PCIe card is inserted.

    Rex
  • 0 in reply to Rex Chang
    Intellectual 270 points

    We have XIO2001 chipset connected to the AM572X processor over PCIe interface and on other side of XIO2001 there are 2-mPCI card connected.

    In our case the processor configures XIO2001 over PCIe during boot-up. We don't have separate driver for XIO2001. For Power saving we wanted to turn-on the processor first and then enable XIO2001 power. When we do this XIO2001 is not getting detected over PCIe interface.

    Below is the flow for our system.

    AM572X--->XIO2001-->mPCI card(2nos)

    Thanks

    Amrendra

  • 0 in reply to Amrendra Kumar
    TI__Guru 50170 points
    Hi, Amrendra,

    I think this is hot pluggable feature, and don't think it is supported in both hardware and software.

    Rex
  • 0 in reply to Rex Chang
    TI__Guru 50170 points
    Hi, Amrendra,

    I just checked internally. This is not hot-pluggable. Once the power to XIO gets turned on and it comes out of reset, the RC should be able to enumerate the bridge and all downstream devices as part of a PCI bus (re)scan. This is too specific to this hardware design and TI has no way to test it using existing platforms.

    Rex
  • 0 in reply to Rex Chang
    TI__Guru 50170 points
    Hi, Amrendra,

    TI Hardware Engineer believes it supports a secondary downstream bus reset. Enumeration should look like this:

    XIO powered.
    (Wait)
    RC asserts PCIe reset to XIO.
    (Wait)
    RC performs bus scan, enumerates "new" XIO bridge.
    RC writes XIO PCI PRST# bit. Downstream PCI devices are reset.
    (Wait)
    RC (re)performs bus scan, enumerates "new" PCI devices.

    Rex
  • 0 in reply to Rex Chang
    Intellectual 270 points

    Hi Rex

    In our system reset to XIO2001 is controlled through processor(AM572X) board.  We are powering up the processor board first then XIO2001 board and then assert reset to  XIO2001. This steps doesn't goes and rescan the devices on downstream bus.

    Does RC stand for(resistor and capacitor) circuit on reset line.

    Thanks

    Amrendra

  • 0 in reply to Amrendra Kumar
    TI__Guru 50170 points

    Hi, Amrendra,

    The Root Complex does not do rescan currently. It expects the End Point being up already. We suggested the steps in my early post to be implemented. Unfortunately, TI has no way to test the steps using existing hardware.

    Rex

  • 0 in reply to Rex Chang
    Intellectual 270 points

    Hi Rex

    Need some clarification on your previous input, my queries are inline below.

    XIO powered.
    (Wait)

    Amrendra: Is there any minimum time recommended for wait time?


     RC asserts PCIe reset to XIO.
    (Wait)

    Amrendra: When you say PCIe reset to XIO, is that mean asserting PERSTn(H11) signal? or It is some different.


    RC performs bus scan, enumerates "new" XIO bridge.

    Amrendra: I assume this scan is being done automatically or need to do anything from processor side.


    RC writes XIO PCI PRST# bit. Downstream PCI devices are reset.
    (Wait)

    Amrendra:XIO2001 on our board runs with default configuration. Is PCIe driver from processor can write on XIO2001 specific registers.


    RC (re)performs bus scan, enumerates "new" PCI devices.

  • 0 in reply to Amrendra Kumar
    TI__Guru 50170 points
    Hi, Amrendra,

    Because the design is very specific with XIO involved, we don't have specific info on how it should work. We believe the XIO supports a secondary downstream bus reset. Therefore, the hardware engineer envisioned and suggested the steps for enumeration.

    The scan would be automatically if the EP is up before RC. Since the EP comes up after RC is up, and RC already done the scan, so the scan in the steps will be a re-scan which needs to be coded in the logic.

    Rex
  • 0 in reply to Amrendra Kumar
    Intellectual 270 points

    Hi Rex

    How to perform the steps "RC writes XIO PCI PRST# bit. Downstream PCI devices are reset" mentioned in previous post?

    Will this be done over PCIe interface from RC?

    Thanks

    Amrendra

  • 0 in reply to Amrendra Kumar
    TI__Guru 50170 points
    Hi, Amrendra,

    I looked up the XIO2001 User's Guide, do you think the SRST bit of the Bridge Control Register at offset 0x3E would work?

    Rex
  • 0 in reply to Rex Chang
    Intellectual 270 points

    Hi Rex

    That's right, but right now we are not controlling/modifying any registers of XIO2001 from RC. XIO2001 is running with default settings. How we can modify the XIO2001 registers from RC?

    XIO2001 has got a I2C master interface so we can't control that from RC. Can we modify XIO2001 registers over PCIe interface from RC?

    Thanks

    Amrendra

  • 0 in reply to Amrendra Kumar
    TI__Guru 50170 points
    Hi, Amrendra,

    Please refer to AM572x TRM, www.ti.com/.../spruhz6h.pdf. All endpoint device registers are memory mapped to PCIE_SSx on AM572x device.

    Rex