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Whethere DM6467 can support SXGA just using TVP7002 and DM6467?

Qixiang Han
Prodigy 20 points
Other Parts Discussed in Thread: TVP7002

hello everyone, these days, I am serching the solution for SXGA input for DM6467, I have found that most parameters of capturing TV vedio signals can be modified by software, that is to say ,  when capturing the BT.1120 and 656 vedio, we can customize the horizontal and vertical size of the vedio. TVP7002 can capture the SXGA vedio and then insert  the sav eav flag into data stream.  I think it's possible that DM6467 can capture the SXGA (with embedded sync flag from TVP7002),but I am not sure.

  • 0
    TI__Intellectual 785 points

    You are correct. Since the video size parameters are programmable, you can enter any size up to the maximum permitted by the hardware registers. SXGA (1280x1024) is within the size DM6467 can handle.

    You will need to configure the TVP7002 to output 16-bit Y/C data with embedded sync. You will then need to set the DM6467 for 16-bit capture, 1280 x 1024 progressive video, with the vertical blanking timings timings to match the incoming video.

  • 0 in reply to ToddHiers
    TI__Genius 16810 points

    Below are TVP7002 settings that should work for 1280x1024 SXGA60Hz, 4:2:2 YCbCr out with embedded syncs.  The TVP input MUX settings may not be configured correctly for your board. You will need to use a processor that supports a 108Mhz input pixel clock.

     

    BEGIN_DATASET  // Appended by WinVCC4 v4.50a.  Saved all registers.

    DATASET_NAME,"TVP7002_SXGA60Hz-108MHz HS/VSin +/+ 4:2:2 embedded syncs RGB>YCbCr"

    //TVP7000
    WR_REG,TVP7000,0x01,0x01,0x69 // PLL DIVMSB      1688 pix/line            
    WR_REG,TVP7000,0x01,0x02,0x80 // PLL DIVLSB
    WR_REG,TVP7000,0x01,0x03,0xA0 // PLL CONTROL                
    WR_REG,TVP7000,0x01,0x04,0x80 // PHASE SEL(5) CKDI CKDI DIV2
    WR_REG,TVP7000,0x01,0x05,0x06 // CLAMP START                
    WR_REG,TVP7000,0x01,0x06,0x10 // CLAMP WIDTH
    WR_REG,TVP7000,0x01,0x07,0x70 // HSYNC OUTPUT WIDTH - 112
    WR_REG,TVP7000,0x01,0x08,0x3C //Blue Fine Gain
    WR_REG,TVP7000,0x01,0x09,0x3C //Green Fine Gain
    WR_REG,TVP7000,0x01,0x0A,0x3C //Red Fine Gain
    WR_REG,TVP7000,0x01,0x0B,0x80 //Blue Fine Offset
    WR_REG,TVP7000,0x01,0x0C,0x90 //Green Fine Offset
    WR_REG,TVP7000,0x01,0x0D,0x80 //Red Fine Offset


    WR_REG,TVP7000,0x01,0x0E,0x24 // SYNC CONTROL    HSout+ VSout+
    WR_REG,TVP7000,0x01,0x0F,0x2E // PLL and CLAMP CONTROL bit0 (0= HSPO by chip)
    WR_REG,TVP7000,0x01,0x10,0x58 // SOG Threshold-(RGB Clamp)
    WR_REG,TVP7000,0x01,0x11,0x40 // Sync Separator Threshold
    WR_REG,TVP7000,0x01,0x12,0x01 // PRE_COAST                  
    WR_REG,TVP7000,0x01,0x13,0x00 // POST_COAST
    WR_REG,TVP7000,0x01,0x15,0x43 // Output Formatter

    WR_REG,TVP7000,0x01,0x17,0x00 // MISC Control 2  FID out, Enable Outputs
    WR_REG,TVP7000,0x01,0x18,0x11 // Clock polarity  
    WR_REG,TVP7000,0x01,0x19,0xAA // INPUT MUX SELECT,    RGB CH3 selected      
    WR_REG,TVP7000,0x01,0x1A,0xCA // INPUT MUX SELECT, HSYNC_A and VSYNC_A selected, SOG and Clamp Filter
    WR_REG,TVP7000,0x01,0x21,0x0D // HSOUT START
    WR_REG,TVP7000,0x01,0x22,0x00 //               
                    
    WR_REG,TVP7000,0x01,0x26,0x80 // ALC RED and GREEN LSB      
    WR_REG,TVP7000,0x01,0x28,0x53 // AL FILTER Control          
    WR_REG,TVP7000,0x01,0x2A,0x87 // Enable FINE CLAMP CONTROL
    WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL-SOG ON
    WR_REG,TVP7000,0x01,0x2C,0x50 // ADC Setup
    WR_REG,TVP7000,0x01,0x31,0x18 // ALC PLACEMENT
    WR_REG,TVP7000,0x01,0x35,0x00 // VSout Align
    WR_REG,TVP7000,0x01,0x36,0x00 // Sync Bypass
    WR_REG,TVP7000,0x01,0x3D,0x06 // Line Length Tolerance (Pixel Tolerance)

    // Embedded sync setup

    WR_REG,TVP7000,0x01,0x40,0x83 // AVID Start  27+HS+Hbp = 27+112+248=387(183h)
    WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start 
    WR_REG,TVP7000,0x01,0x42,0x87 // AVID  Stop AVID Strt + Act Pix +4 =387+1280+4 =1671 (687h)
    WR_REG,TVP7000,0x01,0x43,0x06 // AVID Stop
    WR_REG,TVP7000,0x01,0x44,0x01 // VBLK F0 Offset Vfp=1
    WR_REG,TVP7000,0x01,0x45,0x01 // VBLK F1 Offset
    WR_REG,TVP7000,0x01,0x46,0x2A // VBLK F0 Duration  VBLK=42 lines
    WR_REG,TVP7000,0x01,0x47,0x2A // VBLK F1 Duration


    END_DATASET

  • 0 in reply to Larry Taylor
    Prodigy 20 points

    Larry Taylor,Thank you very much