RTOS: C6657 GPIO interrupt in tirtos

dario iannaccio

Intellectual 870 points

Other Parts Discussed in Thread: SYSBIOS, TMS320C6657

Tool/software: TI-RTOS

Hi,

I have developed a big test application for a custom board. In this environment we will use

an not defined GPIO (0-15) as interrupt external source. In this moment I use evaluation board and

I have developed a TI RTOS task with a little switch placed on test_PH1 connector (GPIO15).

When the ISR works all the other part of system is blocked on Task_sleep function (but I suppose

that all the TI RTOS is on the blocked status). I have used the following TI RTSC libraries:

EDMA3 2.12.2
IPC 3.44.0.00
NDK 2.25.0..9
SYSBIOS 6.46.1.38
PDK 2.0.4
XCDTools 3.32.0.06
CCS TI v8.1.0 (CCS 6.1.3.00034)

The ISR code follows:

******************************** C file:************************

#include <ti/csl/src/intc/csl_intcAux.h>

#include <ti/csl/csl_chip.h>
#include <ti/csl/csl_chipAux.h>
#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/csl/csl_gpioAux.h>

//#define IRQ_SIMUL

typedef struct event2gpio_s
{
   uint32_t gpio;
   uint32_t eventID;
} event2gpio_t;

volatile int a = 0;

CSL_GpioHandle              hGpio = NULL;
const event2gpio_t myGpio2Event[] =
{
{ 0, CSL_GEM_PCIEXPRESS_MSI_INTN_PLUS_2 }, // DO NOT USE
{ 1, CSL_GEM_PCIEXPRESS_MSI_INTN_PLUS_6 }, // DO NOT USE
{ 2, CSL_GEM_GPINT2 },
{ 3, CSL_GEM_GPINT3 },
{ 4, CSL_GEM_GPINT4 },
{ 5, CSL_GEM_GPINT5 },
{ 6, CSL_GEM_GPINT6 },
{ 7, CSL_GEM_GPINT7 },
{ 8, CSL_GEM_GPINT8 },
{ 9, CSL_GEM_GPINT9 },
{ 10, CSL_GEM_GPINT10 },
{ 11, CSL_GEM_GPINT11 },
{ 12, CSL_GEM_GPINT12 },
{ 13, CSL_GEM_GPINT13 },
{ 14, CSL_GEM_GPINT14 },
{ 15, CSL_GEM_GPINT15 }
};

static void GPIO02InterruptHandler(void *arg)
{
   /* Clear the event ID. */
   CSL_intcEventClear((CSL_IntcEventId)arg);
   a++;
}

CSL_IntcContext             intcContext;
CSL_IntcEventHandlerRecord EventHandler[30];
CSL_IntcObj                 intcObj;
CSL_IntcHandle              hTest;
CSL_IntcGlobalEnableState   state;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam               vectId;

// GPIO irq design base: e2e.ti.com/.../374048
/*******************************************************************************
**                      Global Function                                       **
*******************************************************************************/
Void mainFPGA(UArg arg0, UArg arg1)
{
   int                         bankNum = 0;
#ifdef IRQ_SIMUL
   int                         cnt = 1000;
   int                         pinNum = FPGA_GPIOIRQ;
#else
   int                         pinNum = 15;
#endif
   int                         aLocal = 0;

   DBG_PRINTF("Start %s taskname \"%s\"",
              __func__, FPGATASKNAME/*Task_Handle_name(Task_self())*/);

   a = 0;
   bankNum = 0; // Trigger pinNum in Core0

   if (pinNum > SIZEOF(myGpio2Event))
   {
      DBG_PRINTF("Error: pinNum=%d is too big", pinNum);

      return;
   }
   else if (pinNum < 2)
   {
      DBG_PRINTF("Error: pinNum=%d is too little", pinNum);

      return;
   }

   /************************************************
    *************** INTC Configuration *************
    ************************************************/

   // INTC module initialization
   intcContext.eventhandlerRecord = EventHandler;
   intcContext.numEvtEntries      = 10;
   if (CSL_intcInit(&intcContext) != CSL_SOK)
   {
      DBG_PRINTF("Error: GEM-INTC initialization failed");

      return;
   }

   // Enable NMIs
   if (CSL_intcGlobalNmiEnable() != CSL_SOK)
   {
      DBG_PRINTF("Error: GEM-INTC global NMI enable failed");

      return;
   }

   /* Enable global interrupts */
   if (CSL_intcGlobalEnable(&state) != CSL_SOK)
   {
      DBG_PRINTF("Error: GEM-INTC global enable failed");

      return;
   }

   vectId = CSL_INTC_VECTID_4;
   hTest = CSL_intcOpen(&intcObj, myGpio2Event[pinNum].eventID, &vectId , NULL);
   if (hTest == NULL)
   {
      DBG_PRINTF("Error: GEM-INTC Open failed");

      return;
   }

   DBG_PRINTF("Debug: GEM-INTC INT%d EventID%d", hTest->vectId, hTest->eventId);

   /* Register an call-back handler which is invoked when the event occurs. */
   EventRecord.handler = &GPIO02InterruptHandler;
   EventRecord.arg     = hTest;
   if (CSL_intcPlugEventHandler(hTest, &EventRecord) != CSL_SOK)
   {
      DBG_PRINTF("Error: GEM-INTC Plug event handler failed");

      return;
   }

   /* Enabling the events. */
   if (CSL_intcHwControl(hTest, CSL_INTC_CMD_EVTENABLE, NULL) != CSL_SOK)
   {
      DBG_PRINTF("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed");

      return;
   }

   DBG_PRINTF("Debug: GEM-INTC Configuration Completed");

   // Open the CSL GPIO Module 0
   hGpio = CSL_GPIO_open(0);
#ifdef IRQ_SIMUL
   // Set GPIO pin number pinNum as an output pin
   CSL_GPIO_setPinDirOutput(hGpio, pinNum);
#endif
#ifdef RISING
#ifdef IRQ_SIMUL
   CSL_GPIO_clearOutputData(hGpio, pinNum);   //FPGA_GPIOIRQ=0
#endif
   // Set interrupt detection on GPIO pin pinNum to rising edge
   CSL_GPIO_setRisingEdgeDetect(hGpio, pinNum);
#else
#ifdef IRQ_SIMUL
   CSL_GPIO_setOutputData(hGpio, pinNum);     //FPGA_GPIOIRQ=1
#endif
   // Set interrupt detection on GPIO pin pinNum to rising edge
   CSL_GPIO_setFallingEdgeDetect(hGpio, pinNum);
#endif
   // Set GPIO pin number pinNum as an input pin
   CSL_GPIO_setPinDirInput(hGpio, pinNum); //set FPGA_GPIOIRQ to be input

   // Enable GPIO per bank interrupt for bank zero
   CSL_GPIO_bankInterruptEnable(hGpio, bankNum);

   DBG_PRINTF("Debug: GEM-INTC IRQ waiting");
   do
   {
#ifdef IRQ_SIMUL
      Clock0ISR(/*(UArg) */FPGATASKNAME);
      if ((cnt--) == 0)
      {
         cnt = 100;
         CSL_GPIO_setPinDirOutput(hGpio, pinNum);
#ifdef RISING
         // Toggle FPGA_GPIOIRQ pin to trigger GPIO interrupt
         CSL_GPIO_clearOutputData(hGpio, pinNum);   //FPGA_GPIOIRQ=0
         CSL_GPIO_setOutputData(hGpio, pinNum);     //FPGA_GPIOIRQ=1
#else
         // Toggle FPGA_GPIOIRQ pin to trigger GPIO interrupt
         CSL_GPIO_setOutputData(hGpio, pinNum);     //FPGA_GPIOIRQ=1
         CSL_GPIO_clearOutputData(hGpio, pinNum);   //FPGA_GPIOIRQ=0
#endif
      }
      else
      {
         CSL_GPIO_setPinDirInput(hGpio, pinNum); //set FPGA_GPIOIRQ to be input
         // Enable GPIO per bank interrupt for bank zero

     //    Task_sleep(10);// if uncomment this line also this task remain in blocked status

      }
#else

    // Task_sleep(10);// if uncomment this line also this task remain in blocked status

#endif

      if (a != aLocal) // Wait for entering into ISR
      {
#ifdef IRQ_SIMUL
         CSL_GPIO_setPinDirOutput(hGpio, pinNum);
#ifdef RISING
         CSL_GPIO_clearOutputData(hGpio, pinNum);   //FPGA_GPIOIRQ=0
#else
         CSL_GPIO_setOutputData(hGpio, pinNum);     //FPGA_GPIOIRQ=1
#endif
#endif
         DBG_PRINTF("GPIO interrupt occurs a = %d", a);
         aLocal = a;
      }
   } while (global_var->exit_flag == FALSE);

   CSL_intcClose(&intcObj);
   DBG_PRINTF("Exit %s", __func__);

   Task_exit();

   return;
}

******************************** CFG file:************************

var Memory              = xdc.useModule('xdc.runtime.Memory');
var BIOS                = xdc.useModule('ti.sysbios.BIOS');
var Task                = xdc.useModule('ti.sysbios.knl.Task');
var ti_ndk_config_Emac = xdc.useModule('ti.ndk.config.Emac');
var Icmp                = xdc.useModule('ti.ndk.config.Icmp');
var Swi                 = xdc.useModule('ti.sysbios.knl.Swi');
var Timer                 = xdc.useModule('ti.sysbios.hal.Timer');

var SwTimerPrms           = new Timer.Params();
SwTimerPrms.startMode     = Timer.StartMode_AUTO;
SwTimerPrms.period        = 100000;        // 100,000 uSecs = 100ms
SwTimerPrms.instance.name = "SWTimer";
var SwTimer               = Timer.create(null, '&swthTimerHandler', SwTimerPrms);
Task.common$.namedInstance     = true;

var Clock        = xdc.useModule('ti.sysbios.knl.Clock');
Clock.tickPeriod = 750;
var Sem          = xdc.useModule('ti.sysbios.knl.Semaphore');
var Diags           = xdc.useModule('xdc.runtime.Diags');

var devType         = "c6657";

var Csl = xdc.loadPackage('ti.csl');
Csl.Settings.deviceType      = devType;
Csl.Settings.useCSLIntcLib   = true;

/* Load the OSAL package */
var osType          = "tirtos"
var Osal            = xdc.useModule('ti.osal.Settings');
Osal.osType         = osType;
Osal.socType        = devType;

var Qmss               = xdc.loadPackage('ti.drv.qmss');
var Emac               = xdc.loadPackage('ti.drv.emac');
Emac.Settings.socType = devType;
var Nimu               = xdc.loadPackage('ti.transport.ndk.nimu');
Nimu.Settings.socType = devType;

var LoggerBuf       = xdc.useModule('xdc.runtime.LoggerBuf');
var Exc             = xdc.useModule('ti.sysbios.family.c64p.Exception');
Exc.common$.logger = LoggerBuf.create();
Exc.enablePrint     = true;

var Global    = xdc.useModule('ti.ndk.config.Global');
Global.enableCodeGeneration = false;
var Cache       =   xdc.useModule('ti.sysbios.family.c66.Cache');

var Startup       = xdc.useModule('xdc.runtime.Startup');
var System        = xdc.useModule('xdc.runtime.System');
var Settings      = xdc.useModule('ti.sysbios.posix.Settings');
Settings.supportsMutexPriority = true;

var HeapMem               = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams         = new HeapMem.Params();
heapMemParams.size        = 0x3D000;
heapMemParams.sectionName = "systemHeap";
Program.global.heap0      = HeapMem.create(heapMemParams);

Memory.defaultHeapInstance     = Program.global.heap0;
Program.sectMap["sharedL2"]    = "MSMCSRAM";
Program.sectMap["systemHeap"] = "MSMCSRAM";
Program.sectMap[".sysmem"]     = "MSMCSRAM";
Program.sectMap[".args"]       = "MSMCSRAM";
Program.sectMap[".cio"]        = "MSMCSRAM";
Program.sectMap[".rodata"]     = "MSMCSRAM";
Program.sectMap[".neardata"]   = "MSMCSRAM";
Program.sectMap[".cppi"]       = "MSMCSRAM";
Program.sectMap[".init_array"] = "MSMCSRAM";
Program.sectMap[".qmss"]       = "MSMCSRAM";
Program.sectMap[".cinit"]      = "MSMCSRAM";
Program.sectMap[".bss"]        = "MSMCSRAM";
Program.sectMap[".const"]      = "MSMCSRAM";
Program.sectMap[".text"]       = "MSMCSRAM";
Program.sectMap[".code"]       = "MSMCSRAM";
Program.sectMap[".switch"]     = "MSMCSRAM";
Program.sectMap[".data"]       = "MSMCSRAM";
Program.sectMap[".vecs"]       = "MSMCSRAM";
Program.sectMap["emacComm"]    = "L2SRAM";
Program.sectMap[".far:taskStackSection"] = "L2SRAM";
Program.sectMap[".stack"]      = "L2SRAM";
Program.sectMap["platform_lib"]         = "L2SRAM";
Program.sectMap[".fardata:benchmarking"] = "DDR3";
Program.sectMap[".dstBufSec"] = "L2SRAM";
Program.sectMap[".testData"] = "L2SRAM";
Program.sectMap[".srioSharedMem"] = "MSMCSRAM";

SysStd              = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;

Startup.lastFxns.$add('&EVM_init');

BIOS.taskEnabled         =   true;

var drv      = xdc.loadPackage ("ti.sdo.edma3.drv");
var rm       = xdc.loadPackage ("ti.sdo.edma3.rm");
var Event    = xdc.useModule('ti.sysbios.knl.Event');
var Idle     = xdc.useModule('ti.sysbios.knl.Idle');
var CpIntc   = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
var ECM      = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
var HWI      = xdc.useModule('ti.sysbios.family.c64p.Hwi');
var halCache = xdc.useModule('ti.sysbios.hal.Cache');

ECM.eventGroupHwiNum[0] = 7;
ECM.eventGroupHwiNum[1] = 8;

var Utils = xdc.loadPackage('ti.utils.profiling');
var Pcie    = xdc.loadPackage('ti.drv.pcie');
Pcie.Settings.enableProfiling = true;

BIOS.smpEnabled = true;

Clock.timerId = -1;
Clock.swiPriority = 15;
Global.IPv6 = false;

environment['xdc.cfg.check.fatal'] = 'false';
var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
var Log     = xdc.useModule('xdc.runtime.Log');
var Cppi = xdc.loadPackage('ti.drv.cppi');
var Ipc          = xdc.useModule('ti.sdo.ipc.Ipc');
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
SharedRegion.translate = false;
var memmap = Program.cpu.memoryMap;

Program.sectMap[".my_sect_iram"]   = "L2SRAM";
Program.sectMap[".my_sect_ddr"]    = "L2SRAM";

/* ======== gpio_test.cfg ========/
Task.deleteTerminatedTasks = false;
BIOS.swiEnabled = true;
Program.sectMap[".csl_vect"] = "L2SRAM";
var HeapBuf                     =   xdc.useModule('ti.sysbios.heaps.HeapBuf');
var core                        =   xdc.useModule('ti.sysbios.hal.Core');
var Board = xdc.loadPackage('ti.board');
Board.Settings.boardName = "evmC6657";
var Gpio = xdc.loadPackage('ti.drv.gpio');
Gpio.Settings.socType = devType;
var Uart = xdc.useModule('ti.drv.uart.Settings');
Uart.socType = devType;
Task.checkStackFlag             = false;
var memmap                      = Program.cpu.memoryMap;

************ Console:*******************

I suppose that the HWI CSL_INTC_VECTID_4 is already used in TI RTOS as timer schedule

(or some other using), when I use this vectID the RTOS remains blocked .

If I can't use this vectID which other one I can use?

Where is my mistake ? or I have missed something?

Best Regards

Dario

over 9 years ago

0 dario iannaccio over 9 years ago

Intellectual 870 points

I have configured this task at priority 7 and stack size 0x1000.

This morning I have tried to configure a HWI interrupt in cfg file using CSL_INTC_VECTID_4
as vectID and the configuro has failed (obviously I think this vectID is reserved in ti-RTOS).

Regards
Dario

0 ToddMullanix over 9 years ago in reply to dario iannaccio

TI__Guru* 96960 points

I've moved this to the device forum.

Todd

0 Yordan Kovachev over 9 years ago in reply to ToddMullanix

TI__Guru**** 161600 points

Hi,

RTOS team have been notified. Feedback will be posted here.

Best Regards,
Yordan

0 dario iannaccio over 9 years ago in reply to Yordan Kovachev

Intellectual 870 points

Hi,

today I have resolved the question.

************* C code *****************

/* CSL RL includes */
#include <ti/csl/src/intc/csl_intcAux.h>

#include <ti/csl/csl_chip.h>
#include <ti/csl/csl_chipAux.h>
#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/csl/csl_gpioAux.h>

/* XDCtools Header files */
#include <xdc/cfg/global.h>

/* BIOS Header files */
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>

/* TI-RTOS Header files */
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/board/board.h>

//#define IRQ_SIMUL

volatile int a = 0;

CSL_GpioHandle              hGpio = NULL;

static Void GPIO02InterruptHandler(UArg arg)
{
   Hwi_Params *hwiParams = (Hwi_Params *)arg;

   CSL_intcEventClear((CSL_IntcEventId)(hwiParams->arg));
   a++;
}

int gpioISRConfig(int pinNum)
{
   CSL_IntcGlobalEnableState state;
   int                        bankNum = 0, ret = 0;
#ifdef IRQ_SIMUL
   int                        cnt = 1000;
#endif
   GPIO_v0_HwAttrs            gpio_cfg;
   uint32_t                   eventId;
   Hwi_Params                 hwiParams;
   Hwi_Handle                 myHwi;
   Error_Block                eb;
   uint32_t                   numPins, numPorts;

   a = 0;
   bankNum = 0; // Trigger pinNum in Core0

   GPIO_socGetNumPinsPorts(&numPins, &numPorts);
   if (pinNum > numPins)
   {
      DBG_PRINTF("Error: pinNum=%d is too big", pinNum);

      return -11;
   }
   else if (pinNum < 2)
   {
      DBG_PRINTF("Error: pinNum=%d is too little", pinNum);

      return -12;
   }

   if (GPIO_socGetInitCfg(0/*GPIO_LED0_PORT_NUM*/, &gpio_cfg) == -1)
   {
      DBG_PRINTF("Error: GEM-INTC get gpio cfg failed");

      return -13;
   }

   eventId = gpio_cfg.intCfg[pinNum].eventId;

   // initialize error block and hwiParams to default values
   Error_init(&eb);
   Hwi_Params_init(&hwiParams);
   hwiParams.arg        = (UArg)(&hwiParams);
   hwiParams.enableInt = TRUE;
   hwiParams.eventId    = eventId; // 89;
// hwiParams.priority   = ???
// hwiParams.maskSetting = Hwi_MaskingOption_SELF;

   myHwi = Hwi_create(5, GPIO02InterruptHandler, &hwiParams, &eb);
   if (myHwi == NULL)
   {
      DBG_PRINTF("Error: Hwi create failed");

      return -15;
   }

   DBG_PRINTF("Debug: GEM-INTC Configuration Completed");

   // Open the CSL GPIO Module 0
   hGpio = CSL_GPIO_open(0);
#ifdef IRQ_SIMUL
   // Set GPIO pin number pinNum as an output pin
   CSL_GPIO_setPinDirOutput(hGpio, pinNum);
#endif
#ifdef RISING
#ifdef IRQ_SIMUL
   CSL_GPIO_clearOutputData(hGpio, pinNum);   //FPGA_GPIOIRQ=0
#endif
   // Set interrupt detection on GPIO pin pinNum to rising edge
   CSL_GPIO_setRisingEdgeDetect(hGpio, pinNum);
#else
#ifdef IRQ_SIMUL
   CSL_GPIO_setOutputData(hGpio, pinNum);     //FPGA_GPIOIRQ=1
#endif
   // Set interrupt detection on GPIO pin pinNum to rising edge
   CSL_GPIO_setFallingEdgeDetect(hGpio, pinNum);
#endif
   // Set GPIO pin number pinNum as an input pin
   CSL_GPIO_setPinDirInput(hGpio, pinNum); //set FPGA_GPIOIRQ to be input

   // Enable GPIO per bank interrupt for bank zero
   CSL_GPIO_bankInterruptEnable(hGpio, bankNum);

   DBG_PRINTF("Debug: GEM-INTC IRQ waiting");

   return ret;
}

Void mainFPGA(UArg arg0, UArg arg1)
{
   int    aLocal = 0;
#ifdef IRQ_SIMUL
   int    pinNum = FPGA_GPIOIRQ;
#else
   int    pinNum = 15;
#endif

   DBG_PRINTF("Start %s taskname \"%s\"",
               __func__, FPGATASKNAME/*Task_Handle_name(Task_self())*/);

   if (gpioISRConfig(pinNum) >= 0)
   {
      do
      {
#ifdef IRQ_SIMUL
         if ((cnt--) == 0)
         {
            cnt = 100;
            CSL_GPIO_setPinDirOutput(hGpio, pinNum);
#ifdef RISING
            // Toggle FPGA_GPIOIRQ pin to trigger GPIO interrupt
            CSL_GPIO_clearOutputData(hGpio, pinNum);   //FPGA_GPIOIRQ=0
            CSL_GPIO_setOutputData(hGpio, pinNum);     //FPGA_GPIOIRQ=1
#else
            // Toggle FPGA_GPIOIRQ pin to trigger GPIO interrupt
            CSL_GPIO_setOutputData(hGpio, pinNum);     //FPGA_GPIOIRQ=1
            CSL_GPIO_clearOutputData(hGpio, pinNum);   //FPGA_GPIOIRQ=0
#endif
         }
         else
         {
            CSL_GPIO_setPinDirInput(hGpio, pinNum); //set FPGA_GPIOIRQ to be input
            // Enable GPIO per bank interrupt for bank zero
        //    Task_sleep(10);
         }
#else
         Task_sleep(1000);
#endif
         if (a != aLocal) // Wait for entering into ISR
         {
#ifdef IRQ_SIMUL
            CSL_GPIO_setPinDirOutput(hGpio, pinNum);
#ifdef RISING
            CSL_GPIO_clearOutputData(hGpio, pinNum);   //FPGA_GPIOIRQ=0
#else
            CSL_GPIO_setOutputData(hGpio, pinNum);     //FPGA_GPIOIRQ=1
#endif
#endif
            DBG_PRINTF("GPIO interrupt occurs a = %d", a);
            aLocal = a;
         }

      } while (global_var->exit_flag == FALSE);
   }

   DBG_PRINTF("Exit %s", __func__);

   Task_exit();

   return;
}

****************** Cfg file ***************

var Memory              = xdc.useModule('xdc.runtime.Memory');
var BIOS                = xdc.useModule('ti.sysbios.BIOS');
var Task                = xdc.useModule('ti.sysbios.knl.Task');
var ti_ndk_config_Emac = xdc.useModule('ti.ndk.config.Emac');
var Icmp                = xdc.useModule('ti.ndk.config.Icmp');
var Swi                 = xdc.useModule('ti.sysbios.knl.Swi');
var Timer               = xdc.useModule('ti.sysbios.timers.timer64.Timer');
var ti_sysbios_hal_Timer = xdc.useModule('ti.sysbios.hal.Timer');
var DEV = xdc.useModule('ti.sysbios.io.DEV');
var SwTimerPrms           = new Timer.Params();
SwTimerPrms.startMode     = Timer.StartMode_AUTO;
SwTimerPrms.period        = 100000;        // 100,000 uSecs = 100ms
SwTimerPrms.instance.name = "SWTimer";
var SwTimer               = Timer.create(null, '&swthTimerHandler', SwTimerPrms);
Task.common$.namedInstance     = true;
var Clock        = xdc.useModule('ti.sysbios.knl.Clock');
Clock.tickPeriod = 750;
Clock.swiPriority = 15;
Clock.timerId = -1;           // default
var Sem          = xdc.useModule('ti.sysbios.knl.Semaphore');

var Diags           = xdc.useModule('xdc.runtime.Diags');
var devType         = "c6657";

var Csl = xdc.loadPackage('ti.csl');
Csl.Settings.deviceType      = devType;
Csl.Settings.useCSLIntcLib   = true;

var osType          = "tirtos"
var Osal            = xdc.useModule('ti.osal.Settings');
Osal.osType         = osType;
Osal.socType        = devType;

var Qmss               = xdc.loadPackage('ti.drv.qmss');
var Emac               = xdc.loadPackage('ti.drv.emac');
Emac.Settings.socType = devType;
var Nimu               = xdc.loadPackage('ti.transport.ndk.nimu');
Nimu.Settings.socType = devType;

var Defaults = xdc.useModule('xdc.runtime.Defaults');
var LoggerBuf       = xdc.useModule('xdc.runtime.LoggerBuf');
var Exc             = xdc.useModule('ti.sysbios.family.c64p.Exception');
Exc.common$.logger = LoggerBuf.create();
Exc.enablePrint     = true; /* prints exception details to the CCS console */
var Global    = xdc.useModule('ti.ndk.config.Global');
Global.enableCodeGeneration = false;
var Cache       =   xdc.useModule('ti.sysbios.family.c66.Cache');
var Startup       = xdc.useModule('xdc.runtime.Startup');
var System        = xdc.useModule('xdc.runtime.System');
var Settings      = xdc.useModule('ti.sysbios.posix.Settings');
Settings.supportsMutexPriority = true;

var HeapMem               = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams         = new HeapMem.Params();
heapMemParams.size        = 0x3D000;
heapMemParams.sectionName = "systemHeap";
Program.global.heap0      = HeapMem.create(heapMemParams);

Memory.defaultHeapInstance     = Program.global.heap0;
Program.sectMap["sharedL2"]    = "MSMCSRAM";
Program.sectMap["systemHeap"] = "MSMCSRAM";
Program.sectMap[".sysmem"]     = "MSMCSRAM";
Program.sectMap[".args"]       = "MSMCSRAM";
Program.sectMap[".cio"]        = "MSMCSRAM";
Program.sectMap[".rodata"]     = "MSMCSRAM";
Program.sectMap[".neardata"]   = "MSMCSRAM";
Program.sectMap[".cppi"]       = "MSMCSRAM";
Program.sectMap[".init_array"] = "MSMCSRAM";
Program.sectMap[".qmss"]       = "MSMCSRAM";
Program.sectMap[".cinit"]      = "MSMCSRAM";
Program.sectMap[".bss"]        = "MSMCSRAM";
Program.sectMap[".const"]      = "MSMCSRAM";
Program.sectMap[".text"]       = "MSMCSRAM";
Program.sectMap[".code"]       = "MSMCSRAM";
Program.sectMap[".switch"]     = "MSMCSRAM";
Program.sectMap[".data"]       = "MSMCSRAM";
Program.sectMap[".vecs"]       = "MSMCSRAM";
Program.sectMap["emacComm"]    = "L2SRAM";
Program.sectMap[".far:taskStackSection"] = "L2SRAM";
Program.sectMap[".stack"]      = "L2SRAM";
Program.sectMap["platform_lib"]         = "L2SRAM";
Program.sectMap[".fardata:benchmarking"] = "DDR3";
Program.sectMap[".dstBufSec"] = "L2SRAM";
Program.sectMap[".testData"] = "L2SRAM";
Program.sectMap[".srioSharedMem"] = "MSMCSRAM";

SysStd              = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;
Startup.lastFxns.$add('&EVM_init');

BIOS.taskEnabled         =   true;

var drv      = xdc.loadPackage ("ti.sdo.edma3.drv");
var rm       = xdc.loadPackage ("ti.sdo.edma3.rm");
var Event    = xdc.useModule('ti.sysbios.knl.Event');
var Idle     = xdc.useModule('ti.sysbios.knl.Idle');
var CpIntc   = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
var ECM      = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
var HWI      = xdc.useModule('ti.sysbios.family.c64p.Hwi');
var halCache = xdc.useModule('ti.sysbios.hal.Cache');

ECM.eventGroupHwiNum[0] = 7;
ECM.eventGroupHwiNum[1] = 8;

var Utils = xdc.loadPackage('ti.utils.profiling');
var Pcie    = xdc.loadPackage('ti.drv.pcie');
Pcie.Settings.enableProfiling = true;
Pcie.Settings.socType = devType;

BIOS.smpEnabled = true;
Global.IPv6 = false;

environment['xdc.cfg.check.fatal'] = 'false';
var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
var Log     = xdc.useModule('xdc.runtime.Log');
var Cppi = xdc.loadPackage('ti.drv.cppi');
var Ipc          = xdc.useModule('ti.sdo.ipc.Ipc');
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
SharedRegion.translate = false;
var memmap = Program.cpu.memoryMap;

Program.sectMap[".my_sect_iram"]   = "L2SRAM";
Program.sectMap[".my_sect_ddr"]    = "L2SRAM";

/////////////////////// GPIO IRQ ///////////////////////
Task.deleteTerminatedTasks = true;
BIOS.swiEnabled = true;
Program.sectMap[".csl_vect"] = "L2SRAM";
var HeapBuf                     =   xdc.useModule('ti.sysbios.heaps.HeapBuf');
var core                        =   xdc.useModule('ti.sysbios.hal.Core');
var Board = xdc.loadPackage('ti.board');
Board.Settings.boardName = "evmC6657";
var Gpio = xdc.loadPackage('ti.drv.gpio');
Gpio.Settings.socType = devType;
var memmap                      = Program.cpu.memoryMap;

var HeapBuf                     =   xdc.useModule('ti.sysbios.heaps.HeapBuf');
var Log                         =   xdc.useModule('xdc.runtime.Log');
var exception = xdc.useModule('ti.sysbios.family.c64p.Exception');
exception.enablePrint = true;

////////////////////////// GPIO IRQ end //////////////////////////

BIOS.libType = BIOS.LibType_NonInstrumented;
BIOS.assertsEnabled = false;
BIOS.logsEnabled = false;
Clock.tickSource = Clock.TickSource_TIMER;

***************************Serial Console ***********************************

DigitalProc TestBench SW Ver 0.0.1 Build 46 CPU Freq 1000 MHz DSP's core 1 of 2
DSP hw rev. 0 DSP name "TMS320C6657" Board Name "TMDXEVM6657L"
MAC0: 00:18:30:0A:22:88
00:00:00 00:00:07 PciExMain.c@2223:   Start PciExMain taskname "PciExTask"
00:00:00 00:00:00 PciExMain.c@2258:   Version #: 0x02020007; string PCIE LLD Revision: 02.02.00.07:Dec 13 2016:16:29:29
00:00:00 00:00:00 SrioMain.c@1241:   Start SrioTask taskname "SrioTask"
00:00:00 00:00:00 SrioMain.c@1249:   Executing the SRIO Unit Tests on the DEVICE
00:00:00 00:00:00 SrioMain.c@1261:   Debug(Core 0): System Initialization for CPPI & QMSS
00:00:00 00:00:00 SrioMain.c@697:   Debug(Core 0): Queue Manager and CPPI are initialized.
00:00:00 00:00:00 SrioMain.c@698:   Debug(Core 0): Host Region 0x866f80
00:00:00 00:00:00 SrioMain.c@1289:   Debug(Core 0): SRIO Driver has been initialized
00:00:00 00:00:00 QueueHandler.c@95:   0 messages are currently on the /SrioTask queue
00:00:00 00:00:00 EthMain.c@281:   Start EthTask taskname "EthTask"
Network Added: If-1: 192.168.0.8
00:00:00 00:00:00 PlatformTest.c@1598:   Start PlatMsgCmd taskname "PlatTask"
00:00:00 00:00:00 QueueHandler.c@95:   0 messages are currently on the /PlatTask queue
00:00:00 00:00:00 CLI.c@1284:   Start ColiTask taskname "ColiTask"
Write "quit" or "exit" for exit
PROMPT:>
Unknown command ("")
To see the commands writes:"help"
PROMPT:>
00:00:00 00:00:00 CLI.c@1352:   Start CliRecTask taskname "ColiTask"
00:00:00 00:00:00 QueueHandler.c@95:   0 messages are currently on the /ColiRecTask queue
00:00:00 00:00:00 SwTimer.c@425:   Start SwTmrTask taskname "SwTmrTask"
00:00:00 00:00:00 FPGAInterrupt.c@669:   Start mainFPGA taskname "FpgaTask"
00:00:00 00:00:00 FPGAInterrupt.c@271:   Debug: GEM-INTC Configuration Completed
00:00:00 00:00:00 FPGAInterrupt.c@298:   Debug: GEM-INTC IRQ waiting
Unknown command ("")
To see the commands writes:"help"
PROMPT:>
00:00:03 00:00:03 FPGAInterrupt.c@710:   GPIO interrupt occurs a = 10
00:00:04 00:00:01 FPGAInterrupt.c@710:   GPIO interrupt occurs a = 27

Unknown command ("")
To see the commands writes:"help"
PROMPT:>
............

************ Log on PC *************

....
64 bytes from 192.168.0.8: icmp_seq=13703 ttl=255 time=0.153 ms
64 bytes from 192.168.0.8: icmp_seq=13704 ttl=255 time=0.153 ms
64 bytes from 192.168.0.8: icmp_seq=13705 ttl=255 time=0.153 ms
64 bytes from 192.168.0.8: icmp_seq=13706 ttl=255 time=0.144 ms
64 bytes from 192.168.0.8: icmp_seq=13707 ttl=255 time=0.145 ms
64 bytes from 192.168.0.8: icmp_seq=13708 ttl=255 time=0.153 ms
64 bytes from 192.168.0.8: icmp_seq=13709 ttl=255 time=0.152 ms
...

The solution is not use (anymore) the CSL_intcInit / CSL_intcGlobalNmiEnable /
CSL_intcOpen / CSL_intcPlugEventHandler / CSL_intcHwControl functions (intc module)

Best Regards,

Dario

Processors

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RTOS: C6657 GPIO interrupt in tirtos