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ISP / CCDC raw (custom) capture with ISP vsync / hsync as master

CoolAJ86
Intellectual 680 points

I'm developing with the gumstix / openembedded linux-omap-psp branch of the kernel.

I've created a driver using a modified version of the mt9t111 module and board-beagleboard-camera.c. I've set cam_hs and cam_vs to be outputs rather than inputs, and I'm trying to figure out which kernel structs (and hence registers) I need to modify in order for them to actually output a signal rather than just sitting low.

  • 0
    TI__Genius 15510 points

    While I'm not a camera/ISP expert, why are you setting cam_hs and cam_vs as outputs? Looking at the TRM they are bidirectional. And u-boot sets them to input enable (which basically means bidirectional):

     /*CAMERA*/\
            MUX_VAL(CP(CAM_HS),             (IEN  | PTU | EN  | M0)) /*CAM_HS */\
            MUX_VAL(CP(CAM_VS),             (IEN  | PTU | EN  | M0)) /*CAM_VS */\

    Also, since this is the gumstix board you might want to ask questions over at beagleboard.org.

    Steve K.

  • 0 in reply to Steve Kipisz
    Intellectual 680 points

    Thanks for the u-boot info.

    I'm not using anything gumstix specific (beagleboard is a different company, different board, btw). I'm using the lines that they pull out from the omap to a nice ribbon cable where I've attached a custom capture device which is hsync/vsync slave.

    According to the spruf98g that I read through they are either input xor output, but not bidirectional. Perhaps I misunderstood. In either case, setting them as output makes me feel better, because that's what I need.

    It seems that the registers that needed setting were CCDC_SYN_MODE, CCDC_PIX_LINES, and CCDC_HD_VD_WID. I haven't quite got things working right, still, but I'm seeing a signal now and I'm getting there.

  • 0 in reply to CoolAJ86
    TI__Intellectual 1280 points

    Please reference section 12.5.4.6.1.2(Timing Generator and Frame Settings of spruf98f TRM for OMAP35x.  Cam_hs and Cam_vs are IOs with default set as Input as Steve mentioned.    Register, CCDC_SYN_MODE, bit 0 (VDHDOUT) sets signal direction for cam_hs and cam_vs signals and HDPOL and VDPOL set signal polarity which is positive by default.  Please also refer to Section 12.5.4.1.2, CCDC register setup,  which discusses required CCDC configuration parameters.

  • 0
    Intellectual 680 points 

    http://fastr.github.com/articles/CCDC-hs-vs-as-output-via-uBoot.html
    It can be done via the kernel by setting CONFIG_OMAP3_MUX and then a line like

    OMAP3_MUX(CAM_HS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),

    or via uboot by finding overo.h and changing `CAM_HS` and `CAM_VS` from IEN (input enable) to IDIS (input disable)