Compiler: C66x Caching

MotorControl

Tool/software: TI C/C++ Compiler

Sorry for this basic question.

I have a simple loop program, which I would like to run on the evmK2G from I$. What are the necessary steps. I did read SPRUGY8.

1) C66x CSL Command Sequence to Enable Caching:

CACHE_enable(CACHE_CE00); // as defined in SPRUGY8

CACHE_setL2Size(CACHE_256KCACHE); // as defined in SPRUGY8

Q1: What does CACHE_CE00 stands for ?

Q2: SPRUGY8 also says, that the program fetches are always cached in L1P, regardless of the MAR setting. So is this CACHE_ENABLE command obsolete.

Q3: Do I have to set L1 cache size with "CACHE_L1dSetSize();

2) define a section in program:

#pragma CODE_SECTION(getA, ".section_name")

int getA(int i) {

// some code …

}

int main(void) {

...

Q4: Is this a possible way? I see the .section_name in the map file.

3) C66x Linker File

MEMORY

{

L2_SRAM_0 : o = 0x00800000 l = 0x00080000 /* 512kB internal SRAM */

L2_SRAM_1 : o = 0x00880000 l = 0x00080000 /* 512kB internal SRAM */

MSMC_SRAM : o = 0x0C000000 l = 0x00100000 /* 1MB MSMC Shared SRAM */

DDR0 : o = 0x81000000 l = 0x80000000 /* 2GB external DDR0 */

CE0 : o = 0x80000000 l = 0x01000000

}

SECTIONS

{

.text > L2_SRAM_0

[snip]

.section_name > CE0

}

Q5: Are these valid entries for my problem ?

In any case, the runtime remains the same, however I try to turn on the I$.

Any help is highly appreciated. Thank you for your time. Sorry again for this basic question.

over 8 years ago

0 Rahul Prabhu over 8 years ago

TI__Guru** 116170 points

Motorcontrol,

MotorControl said:
Q1: What does CACHE_CE00 stands for ?

CACHE_CE00 Macro was defined for earlier DSP CSL to turn on the cache for the region (0x80000000 to 0x80FFFFFF) in earlier versions of CSL. This Macro and API have been changed for C66x to correspond to appropriate MAR register. The same can be done using following API on K2G :

CACHE_enableCaching(CACHE_MAR128);

MotorControl said:
Q2: SPRUGY8 also says, that the program fetches are always cached in L1P, regardless of the MAR setting. So is this CACHE_ENABLE command obsolete.

there is clarification provided to the that statement later in the document. The cacheability settings of external memory addresses (through the MAR bits) only affect L1D and L2 caches on C66x devices; that is, program fetches to external memory addresses are always cached in L1P, regardless of the cacheability setting. This is not the case on C64x devices, where the settings affects all caches, L1P, L1D, and L2.

This means that you need to enable Caching only for data for instruction/code this is always cached in L1P but you can change the cached size of L1P

MotorControl said:
Q3: Do I have to set L1 cache size with "CACHE_L1dSetSize();

this is not always required but if you want to partition that memory as cache and SRAM then that will be required.

MotorControl said:
Q4: Is this a possible way? I see the .section_name in the map file.

Yes, you can use the code provided to place a function in specific memory region as you specified. You can always look at the .map file after the .out builds to see if the function was placed in the correct memory section.

Refer to compiler documentation for details:

MotorControl said:
Q5: Are these valid entries for my problem ?

I don`t see any issues with your implementation, do you see any issues when you build this code and look at the map file?

Regards,

Rahul

0 MotorControl over 8 years ago in reply to Rahul Prabhu

Prodigy 190 points

Rahul,

thank you so much for spending your time on this.

Is my understanding correct, when you generate a default “hello world” loop in CCS for C66X (K2G), then the first pass will be executed from external memory, and the second runs from L1P.

I assumed I have to do some basic cache enabling.

My oscilloscope says, that the runtime of the first pass is identical to the following ones. So I still don’t know what to do.

Regards, MotorControl

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Compiler: C66x Caching