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NAND ECC support for DM6446 DSP

Other Parts Discussed in Thread: OMAP3530

Does the DM6446 ROM support 4-bit ECC when interfacing to SLC NAND?

We have a customer who is currently using this DSP with a 1-bit ECC 2Gb SLC NAND part from Micron p/n: MT29F2G08AADWP.  However, Micron has gone through a die shrink on this part (50nm to 34nm) which changed ECC requirement from 1-bit to 4-bit

Basically, will the DM6446 ROM support NAND device migration going from MT29F2G08AADWP.D (50nm 1-bit ECC) to MT29F2G08ABAEAWP.E (34nm 4-bit ECC)?

  • Terry,

     

    No.  The DM6446 ROM boot loader only supports 1-bit of hardware ECC in the device.  No, there is no hardware ECC support for NANDs whose ECC requirements are going higher than what is available in the NAND controller of the device.  NAND manufacturers that we have spoken to are advocating that customers go to managed NAND products such as eMMC, eSD and others if a given embedded processor supports booting via those interfaces (MMC, SD, etc...). 

    That being said, given that this device does not support ROM boot from MMC or SD, you could boot from a small NOR flash and then switch to NAND flash after boot.  Your biggest challenge will be getting past the ROM boot, but the Linux kernel boot and such relies on software ECC which should support the 4-bit ECC needed for your new NAND flash.

     

     

  • FYI, some of the NAND devices that I've seen that require 4-bit ECC have spec'd the first block such that it can utilize 1-bit ECC for 1000 erase cycles.  This would allow you to still boot from these devices using 1-bit ECC.

    Of course, even with that issue out of the way you will immediately run into the issue of not having 4-bit ECC hardware!  I suppose that could be addressed by software ECC.  (Some patches for 4-bit software ECC are being worked on for OMAP3530 and might be at least partially reusable.)  I don't know how much CPU that will chew up.  We recently released an 810 MHz version of the DM6446 so at least there would be an option to get a faster device to counteract the software overhead of the ECC!