OMAP3530: DSS_PCLK phase

Jim Samuels

Other Parts Discussed in Thread: OMAP3530

Hi,

How do I change the phase on the DSS_PCLK with respect to the data? The data is changing on the opposite edge of DSS_PCLK that my video encoder wants.

over 8 years ago

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi,

This is a legacy device and it is no longer supported.. However, I've someone from the omap3 forum support team, to have s look at this.

Best Regards,
Yordan

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

Hi Jim,

You can configure pixel clock polarity via DSI_CTRL register VP_CLK_POL field.
0x0: The DSI Protocol Engine module captures the data on the VP on the pixel clock falling edge. The module connected to the VP must drive the data on the pixel clock rising edge.
0x1: The DSI Protocol Engine module captures the data on the VP on the pixel clock raising edge. The module connected to the VP must drive the data on the pixel clock falling edge.
For more details check OMAP3530 TRM Table 15-393.

BR
Tsvetolin Shulev

0 Jim Samuels over 8 years ago in reply to Cvetolin Shulev-XID

Prodigy 80 points

Thank you. We will give it a shot.

0 Robert Dejpour68 over 8 years ago in reply to Cvetolin Shulev-XID

Prodigy 10 points

Hi Cvetolin,

I am actually interested to invert the DSS_PCLK for video output signal. The VP_CLK_POL is used for receiver/camera I need the to invert DSS_PCLK for external.

Regards - Robert

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OMAP3530: DSS_PCLK phase