OMAP-L138: Sample code to connect with FPGA using EMIFA

Hi Miyashiro-san
Unfortunately we do not have any development boards and therefore any code examples to show case EMIFA to FPGA
We have seen many customers implement this on their own primarily using the EMIFA chapter from the TRM.

You may also want to explore our 3P Critical Link , who have a SOM that show cases this solution and may have the required software to enable this

www.criticallink.com/.../

Regards
Mukul

The EMIFA controller comes out of reset setup for async access. Look into the TRM for reset values for CEnCFG. There is not much to configuring EMIFA for access to a memory mapped device. The StarterWare EMIFA driver is a bit more complicated than it need. I don't bother with it. The example below accesses the EMIFA registers directly rather using the StarterWare APIs. The StarterWare style of pinmux code is very wordy but it is what it is. You could reduce this down to single accesses to a pinmux register rather than multiple accesses to the same register. Example assumes a 16-bit wide bus to FPGA. I have not compiled this code snippet.

void fpga_init(void)
{
  PSCModuleControl(SOC_PSC_0_REGS,
                   HW_PSC_EMIFA,
                   PSC_POWERDOMAIN_ALWAYS_ON,

                   PSC_MDCTL_NEXT_ENABLE);    


  HWREG(SOC_SYSCFG_0_REGS+SYSCFG0_PINMUX(5) =
  (HWREG(SOC_SYSCFG_0_REGS+SYSCFG0_PINMUX(5)&
                            ~SYSCFG_PINMUX5_PINMUX5_31_28)|
                            (SYSCFG_PINMUX5_PINMUX5_31_28_EMA_BA0<<
                             SYSCFG_PINMUX5_PINMUX5_31_28);
  /* Repeat for EMA_A0-EMA_A? and EMA_D0-EMA_D15, any other EMA signals */
  
  /* Miniimally set the CFG register. Set to maximum times if unsure. */
  HWREG(SOC_EMIFA_0_REGS+EMIFA_CE3CFG)
    = 0x00 << 31 /* 0-1  SS */
    | 0x00 << 30 /* 0-1  EW */
    | 0x0F << 26 /* 0-F  W_SETUP */
    | 0x3F << 20 /* 0-3F W_STROBE */
    | 0x07 << 17 /* 0-7  W_HOLD */
    | 0x0F << 13 /* 0-F  R_SETUP */
    | 0x3F <<  7 /* 0-3F R_STROBE */
    | 0x07 <<  4 /* 0-7  R_HOLD */
    | 0x03 <<  2 /* 0-3  TA */
    | 0x01 <<  1;/* 0-3  ASIZE, 0=8-bit,1=16-bit */

  /* Now can access at CSn_ADDR */
}

void fpga_set(int i, uint16 v)
{
  volatile uint16 *p = (volatile uint16 *)SOC_EMIFA_CS3_ADDR;
  p[i] = v;
}

uint16 fpga_get(int i)
{
  volatile uint16 *p = (volatile uint16 *)SOC_EMIFA_CS3_ADDR;
  return(p[i]);
}