Hi,
I am Routing the DDR3 for AM3359. I have a single DDR3 Chip.
Reference : AM335x datasheet , Table 7-66. CK and ADDR_CTRL Routing Specification
The table provides a spec for the the data for skew between the address separately , and intra pair skew of the CLK+/- separately.
1) is it not required for the Address and the Clock ( length) to have the same skew of 100 mils ? (is it ok for Addresses to have a nominal AT length of 90 mils and CLK to have 400 mils?) ?
2) The current skew for my CLK's "AT" is about 20 mils. But the AT max length for my CLK is only 75 mils. If I have to match my length , I will not be able to maintain the differential spacing for this small length (such is my constraint). I can think of three options"
a) Leave it as it is - Differential spacing of CLK will be maintained but it will not meet the Skew requirement only for the AT stun
( there is a Via on one end of the 75 mils trace and the termination on the other end, routed in bottom layer)
b) Ensure equal lengths- but differential spacing will NOT be maintained for this AT length of 75 mils. Possible common mode noise radiation?
c) Lengthen ONLY the CLK trace to about 450 mils differentially, and add bumps or curve near the termination end to achieve the 5 mils skew spec ( again some differential spacing will need to violated a little near the termination resistor.)
What would be the best option?
Note: Between TI device to the DDR3 device , I have respected all length and skew constraints.
Thanks