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TMDSEVM6678: Can't get the SPI DMA work!

MN
Intellectual 600 points

Part Number: TMDSEVM6678

Hi,

I'm trying to get an ADC board send data through the SPI to my evaluation board in 4 wire mode.  Taking an example of the SPI DMA loopback and changing it to just send one word to the ADC through SPI does not work and I can't find out why.  I don't see any clock or chip select signal with running my code and it gets stuck in the while loop for transmit interrupt from DMA in "Test_Edma" function.  It seems that nothing is happening.  I'm not sure if I should be able to see a continuous clock on the SPICLK pin or just one clock, but still I don't see anything, and I don't know how to debug this.  Here is the code I'm running;

#include <ti/csl/soc.h>
#include <ti/csl/tistdtypes.h>
#include <ti/csl/csl_chip.h>
#include <ti/csl/csl_edma3.h>
#include <ti/csl/csl_edma3Aux.h>
#include <ti/csl/cslr_spi.h>
#include <ti/csl/soc/c6678/src/cslr_device.h>
#include <spi_common.h>
#include <stdio.h>

#define TEST_ACNT 2
#define TEST_BCNT 1
#define TEST_CCNT 1

#define TEST_SYCTYPE_AB     1
#define TEST_SYCTYPE_A      0

#define BUF_SIZE TEST_BCNT

Uint16 dstBuf[2];
Uint16 srcBuf[2] ={0,0x80};

typedef volatile  CSL_SpiRegs    *CSL_SpiRegsOvly;

void Trigger_Edma_Channels(void)
{
   	// Trigger channel
   	CSL_edma3HwChannelControl(hChannel0,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);

   	// Trigger channel
   	CSL_edma3HwChannelControl(hChannel1,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);

}


void Setup_Edma (Uint32 srcBuf,Uint32 dstBuf)
{

    // EDMA Module Initialization
	CSL_edma3Init(NULL);

 	// EDMA Module Open
    hModule = CSL_edma3Open(&moduleObj,CSL_TPCC_1,NULL,&EdmaStat);


	// SPI Tx Channel Open - Channel 2 for Tx (SPIXEVT)
	chParam.regionNum  = CSL_EDMA3_REGION_GLOBAL;
	chSetup.que        = CSL_EDMA3_QUE_0;
	chParam.chaNum     = CSL_EDMA3_CHA_2;

	hChannel0 = CSL_edma3ChannelOpen(&ChObj0, CSL_TPCC_1, &chParam, &EdmaStat);
	chSetup.paramNum   = chParam.chaNum; //CSL_EDMA3_CHA_2;
    CSL_edma3HwChannelSetupParam(hChannel0,chSetup.paramNum);

	// SPI Rx Channel Open - Channel 3 for Rx (SPIREVT)
	chParam.regionNum  = CSL_EDMA3_REGION_GLOBAL;
	chSetup.que        = CSL_EDMA3_QUE_0;
	chParam.chaNum     = CSL_EDMA3_CHA_3;

	hChannel1 = CSL_edma3ChannelOpen(&ChObj1, CSL_TPCC_1, &chParam, &EdmaStat);
	chSetup.paramNum = chParam.chaNum; //CSL_EDMA3_CHA_3;
    CSL_edma3HwChannelSetupParam(hChannel1,chSetup.paramNum);

	// Parameter Handle Open
	// Open all the handles and keep them ready
	paramHandle0            = CSL_edma3GetParamHandle(hChannel0,CSL_EDMA3_CHA_2,&EdmaStat);
  	paramHandle1            = CSL_edma3GetParamHandle(hChannel1,CSL_EDMA3_CHA_3,&EdmaStat);


    paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(TEST_ACNT,(TEST_BCNT));
	paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(TEST_ACNT,0 );
	paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);
	paramSetup.cCnt         = TEST_CCNT;
	paramSetup.option       = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,CSL_EDMA3_CHA_2,CSL_EDMA3_TCC_NORMAL, \
	      CSL_EDMA3_FIFOWIDTH_NONE,FALSE,CSL_EDMA3_SYNC_A,CSL_EDMA3_ADDRMODE_INCR,CSL_EDMA3_ADDRMODE_INCR);

	paramSetup.srcAddr      = (Uint32)(srcBuf);
	paramSetup.dstAddr      = (Uint32)&(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDAT0);
	paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);

	CSL_edma3ParamSetup(paramHandle0,&paramSetup);

    paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(TEST_ACNT,TEST_BCNT);
	paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(0,TEST_ACNT );
	paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);
	paramSetup.cCnt         = TEST_CCNT;
	paramSetup.option       = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,CSL_EDMA3_CHA_3,CSL_EDMA3_TCC_NORMAL, \
	      CSL_EDMA3_FIFOWIDTH_NONE,FALSE,CSL_EDMA3_SYNC_A,CSL_EDMA3_ADDRMODE_INCR,CSL_EDMA3_ADDRMODE_INCR);
	paramSetup.srcAddr      = (Uint32)&(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIBUF);


	paramSetup.dstAddr      = (Uint32)dstBuf;

	paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);

	CSL_edma3ParamSetup(paramHandle1,&paramSetup);
	Trigger_Edma_Channels();
}

void Test_Edma(void)
{

	// Wait for interrupt
    regionIpr.region  = CSL_EDMA3_REGION_GLOBAL;
	regionIpr.intr    = 0;
	regionIpr.intrh   = 0;
/*	do{
		CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIpr);
	}while ((regionIpr.intr & 0x08) != 0x08);	//channel_3
*/

	do{
		CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIpr);
	}while ((regionIpr.intr & 0x04) != 0x04);	//channel_2

}


void Close_Edma()
{
    CSL_FINST(hModule->regs->TPCC_SECR,TPCC_TPCC_SECR_SECR2,RESETVAL);
  	CSL_FINST(hModule->regs->TPCC_SECR,TPCC_TPCC_SECR_SECR3,RESETVAL);

 	CSL_edma3ChannelClose(hChannel0);
 	CSL_edma3ChannelClose(hChannel1);
 	CSL_edma3Close(hModule);
}

void Setup_SPI (void)
{
    /* Reset SPI */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR0=
        CSL_SPI_SPIGCR0_RESET_IN_RESET<<CSL_SPI_SPIGCR0_RESET_SHIFT;

    /* Take SPI out of reset */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR0=
        CSL_SPI_SPIGCR0_RESET_OUT_OF_RESET<<CSL_SPI_SPIGCR0_RESET_SHIFT;

    /* Configure SPI as master */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR1=
        CSL_SPI_SPIGCR1_CLKMOD_INTERNAL<<CSL_SPI_SPIGCR1_CLKMOD_SHIFT|
        CSL_SPI_SPIGCR1_MASTER_MASTER<<CSL_SPI_SPIGCR1_MASTER_SHIFT;

    /* Configure SPI in 4-pin SCS mode */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIPC0=
        CSL_SPI_SPIPC0_SOMIFUN_SPI<<CSL_SPI_SPIPC0_SOMIFUN_SHIFT|
        CSL_SPI_SPIPC0_SIMOFUN_SPI<<CSL_SPI_SPIPC0_SIMOFUN_SHIFT|
        CSL_SPI_SPIPC0_CLKFUN_SPI<<CSL_SPI_SPIPC0_CLKFUN_SHIFT|
        CSL_SPI_SPIPC0_SCS0FUN0_SPI<<CSL_SPI_SPIPC0_SCS0FUN0_SHIFT;


	/* Take SPI out of Lpbk mode */
	((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR1 |=
		CSL_SPI_SPIGCR1_LOOPBACK_DISABLE<<CSL_SPI_SPIGCR1_LOOPBACK_SHIFT;

    /* Chose SPIFMT0 */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDAT1=
        CSL_SPI_SPIDAT1_DFSEL_FORMAT0<<CSL_SPI_SPIDAT1_DFSEL_SHIFT;
    /* Configure for WAITEN=YES,SHIFTDIR=MSB,POLARITY=HIGH,PHASE=IN,CHARLEN=16*/
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIFMT[0]=
        CSL_SPI_SPIFMT_WAITENA_DISABLE<<CSL_SPI_SPIFMT_WAITENA_SHIFT|
        CSL_SPI_SPIFMT_SHIFTDIR_MSB<<CSL_SPI_SPIFMT_SHIFTDIR_SHIFT|
        CSL_SPI_SPIFMT_POLARITY_LOW<<CSL_SPI_SPIFMT_POLARITY_SHIFT|
        CSL_SPI_SPIFMT_PHASE_DELAY<<CSL_SPI_SPIFMT_PHASE_SHIFT|
        0x1<<CSL_SPI_SPIFMT_PRESCALE_SHIFT|
        0x10<<CSL_SPI_SPIFMT_CHARLEN_SHIFT;

	((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 =
	CSL_SPI_SPIINT0_ENABLEHIGHZ_ENABLE<<CSL_SPI_SPIINT0_ENABLEHIGHZ_SHIFT|
	CSL_SPI_SPIINT0_OVRNINTENA_ENABLE<<CSL_SPI_SPIINT0_OVRNINTENA_SHIFT|
	CSL_SPI_SPIINT0_BITERRENA_ENABLE<<CSL_SPI_SPIINT0_BITERRENA_SHIFT|
	CSL_SPI_SPIINT0_DESYNCENA_ENABLE<<CSL_SPI_SPIINT0_DESYNCENA_SHIFT|
	CSL_SPI_SPIINT0_PARERRENA_ENABLE<<CSL_SPI_SPIINT0_PARERRENA_SHIFT|
	CSL_SPI_SPIINT0_TIMEOUTENA_ENABLE<<CSL_SPI_SPIINT0_TIMEOUTENA_SHIFT|
	CSL_SPI_SPIINT0_DLENERRENA_ENABLE<<CSL_SPI_SPIINT0_DLENERRENA_SHIFT;

    /* Enable communication */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR1|=
        CSL_SPI_SPIGCR1_ENABLE_ENABLE<<CSL_SPI_SPIGCR1_ENABLE_SHIFT;

	((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 |=
		CSL_SPI_SPIINT0_DMAREQEN_ENABLE<<CSL_SPI_SPIINT0_DMAREQEN_SHIFT;

	while(!(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIFLG & 0x00000200));

//	while(!(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIFLG & 0x00000100));

}


void main (void)
{
	
  	//Setup EDMA for SPI transfer
   	Setup_Edma((Uint32)srcBuf,(Uint32)dstBuf);

	//Configure SPI in loopback mode and enable DMA interrupt support
	Setup_SPI();

	//Check EDMA transfer completion status
    	Test_Edma();

	//Close EDMA channels/module  */
	Close_Edma();


	printf("end of test\n");

}

Could someone please help me as I'm really stumped!  I appreciate any response.

  • 0
    Intellectual 600 points
    I also tried setting chip select to both active high and low:
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDEF= CSL_SPI_SPIDEF_CSDEF0_LOW<<CSL_SPI_SPIDEF_CSDEF0_SHIFT;

    and it does not change anything at all. Checking the spi registers everything seems to be as expected, except that the transfer buffer empty bit on SPIFLG goes high and never clears. Please let me know if you have any suggestions to debug.
  • 0 in reply to MN
    Intellectual 600 points

    I desperately need some help please!

  • 0 in reply to MN
    Guru 26430 points

    Looks like th experts are away thinking. My experience is with C6748 not the C6678. Some guesses. You should not increment on SPI tx and rx registers. You should set the FIFO width to match the SPI data width.

        paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(TEST_ACNT,(TEST_BCNT));
    paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(TEST_ACNT,0 );
    paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);
    paramSetup.cCnt         = TEST_CCNT;
    paramSetup.option       = CSL_EDMA3_OPT_MAKE(
                                 CSL_EDMA3_ITCCH_DIS,
                                 CSL_EDMA3_TCCH_DIS,
                                 CSL_EDMA3_ITCINT_DIS,
                                 CSL_EDMA3_TCINT_EN,
                                 CSL_EDMA3_CHA_2,          /*tcc*/
                                 CSL_EDMA3_TCC_NORMAL,
                                 CSL_EDMA3_FIFOWIDTH_16BIT,
                                 CSL_EDMA3_STATIC_DIS,
                                 CSL_EDMA3_SYNC_A,
                                 CSL_EDMA3_ADDRMODE_CONST, /*dam*/
                                 CSL_EDMA3_ADDRMODE_INCR); /*sam*/
    paramSetup.dstAddr      = (Uint32)&(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDAT0);
    paramSetup.srcAddr      = (Uint32)(srcBuf);
    paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
    CSL_edma3ParamSetup(paramHandle0,&paramSetup);

    paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(TEST_ACNT,TEST_BCNT);
    paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(0,TEST_ACNT );
    paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);
    paramSetup.cCnt         = TEST_CCNT;
    paramSetup.option       = CSL_EDMA3_OPT_MAKE(
                                 CSL_EDMA3_ITCCH_DIS,
                                 CSL_EDMA3_TCCH_DIS,
                                 CSL_EDMA3_ITCINT_DIS,
                                 CSL_EDMA3_TCINT_EN,
                                 CSL_EDMA3_CHA_3,          /*tcc*/
                                 CSL_EDMA3_TCC_NORMAL,
                                 CSL_EDMA3_FIFOWIDTH_16BIT,
                                 CSL_EDMA3_STATIC_DIS,
                                 CSL_EDMA3_SYNC_A,
                                 CSL_EDMA3_ADDRMODE_INCR,  /*dam*/
                                 CSL_EDMA3_ADDRMODE_CONST);/*sam*/
    paramSetup.dstAddr      = (Uint32)dstBuf;
    paramSetup.srcAddr      = (Uint32)&(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIBUF);
    paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
    CSL_edma3ParamSetup(paramHandle1,&paramSetup);

  • 0 in reply to Norman Wong
    Intellectual 600 points

    Thanks so much Norman for your response.  Although your advice was very valuable, it didn't change the behavior of my application, at lease as far as I could see.  

    I already got the application run through the end somehow (I can't tell how, I guess the ESR register had its flag on and it cleared after I power cycled the board!), but I still can't see any signals out of SPI.  I thought maybe one byte is so short that I would miss it on oscilloscope, so I made the BCNT 5, to read more data from a larger source buffer, and that made it get stuck at the while loop for interrupt again!  Any idea what's going on?

  • 0 in reply to MN
    Guru 26430 points

    I looked back over my C6748 SPI EDMA code and your original settings were correct. Ignore what I said in the last post. Very sorry about that. This is what I used:

    #define TEST_ACNT 2 /* 1=8-bit or 2=16 bit words */
#define TEST_BCNT 1 /* Number of words */
#define TEST_CCNT 1

paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(TEST_ACNT,TEST_BCNT);
paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(TEST_ACNT,0 ); /*src+=ACNT,dst+=0*/
paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);  /* Use of 0 means ASYNC */
paramSetup.cCnt         = TEST_CCNT;
paramSetup.option       = CSL_EDMA3_OPT_MAKE(
                             CSL_EDMA3_ITCCH_DIS,
                             CSL_EDMA3_TCCH_DIS,
                             CSL_EDMA3_ITCINT_DIS,
                             CSL_EDMA3_TCINT_EN,
                             CSL_EDMA3_CHA_2,          /*tcc*/
                             CSL_EDMA3_TCC_NORMAL,
                             CSL_EDMA3_FIFOWIDTH_NONE,
                             CSL_EDMA3_STATIC_DIS,
                             CSL_EDMA3_SYNC_A,
                             CSL_EDMA3_ADDRMODE_INCR,  /*dam*/
                             CSL_EDMA3_ADDRMODE_INCR); /*sam*/
paramSetup.dstAddr      = (Uint32)&(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDAT1); /*Was SPIDAT0*/
paramSetup.srcAddr      = (Uint32)(srcBuf);
paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
CSL_edma3ParamSetup(paramHandle0,&paramSetup);
 
paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(TEST_ACNT,TEST_BCNT);
paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(0,TEST_ACNT ); /*src+=0,dst+=ACNT*/
paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0); /* Use of 0 means ASYNC */
paramSetup.cCnt         = TEST_CCNT;
paramSetup.option       = CSL_EDMA3_OPT_MAKE(
                             CSL_EDMA3_ITCCH_DIS,
                             CSL_EDMA3_TCCH_DIS,
                             CSL_EDMA3_ITCINT_DIS,
                             CSL_EDMA3_TCINT_EN,
                             CSL_EDMA3_CHA_3,         /*tcc*/
                             CSL_EDMA3_TCC_NORMAL,
                             CSL_EDMA3_FIFOWIDTH_NONE,
                             CSL_EDMA3_STATIC_DIS,
                             CSL_EDMA3_SYNC_A,
                             CSL_EDMA3_ADDRMODE_INCR,  /*dam*/
                             CSL_EDMA3_ADDRMODE_INCR); /*sam*/
paramSetup.dstAddr      = (Uint32)dstBuf;
paramSetup.srcAddr      = (Uint32)&(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIBUF);
paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
CSL_edma3ParamSetup(paramHandle1,&paramSetup);

    I used SPIDAT1 instead SPIDAT0 because of CSHOLD, WDEL, CSNR did not seem to work with SPIDAT0.

    This line might be problematic as it may trigger a transmit.

    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDAT1=
        CSL_SPI_SPIDAT1_DFSEL_FORMAT0<<CSL_SPI_SPIDAT1_DFSEL_SHIFT;

    You need to do a byte write to parts of the SPIDAT1 register to avoid TXDATA part.

    I am not familar this processor. So these question may be silly. Have you enable power and clock to the SPI controller? Is that pinmux or gating of the pins? Are you sure that the pins are not shorted? Can you reassign the pins as GPIOs and toggle them?

    That's all I got. Hopefully some experts will comment.

  • 0 in reply to MN
    Guru 26430 points

    In my C6748 code, the DMA starts when the SPI DMA interrupt is enabled. This line might be too early.

        ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 |=
        CSL_SPI_SPIINT0_DMAREQEN_ENABLE<<CSL_SPI_SPIINT0_DMAREQEN_SHIFT;

    I think it enable and disable should around the wait loop, eg.

        ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 |=
        CSL_SPI_SPIINT0_DMAREQEN_ENABLE<<CSL_SPI_SPIINT0_DMAREQEN_SHIFT;

    do{
        CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIpr);
    }while ((regionIpr.intr & 0x04) != 0x04);   //channel_2

    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 &=
       ~(CSL_SPI_SPIINT0_DMAREQEN_ENABLE<<CSL_SPI_SPIINT0_DMAREQEN_SHIFT);

    However, I used an interrupt handler. Polling might be different.

  • 0 in reply to Norman Wong
    Intellectual 600 points

    Thanks very much Norman.  I've tried many different combinations of these configurations and nothing seems to work.  Having gone back to the original setup, I don't get the same behavior either, and that's frustrating.  Now the problem is that my SER and EMR flags go on right after the SPIINT0_DMAREQEN_ENABLE.  I tried this line:

    CSL_edma3HwChannelControl (hChannel0,CSL_EDMA3_CMD_CHANNEL_CLEARERR,NULL);

    and no luck.  It only clears after hard reset!  I don't quite understand what triggers these errors.  I'd appreciate if you have any inputs for that.

    Also would you please share your code for how you handle the interrupt instead of polling.

    Thanks very much.

  • 0 in reply to MN
    Guru 26430 points
    My code is for the C6748/StarterWare. It would not work with C6678/CSL. As far as I can tell, your settings for PaRAM look correct. The event number and channel numbers look good. The fact you don't see anything on the pins suggest it may be a HW problem. Have you tried a directed polled IO? No EDMA or interrupts. Just SPI setup and write to SPIDAT1 or SPIDAT1 to see if you get anything out of the pins.
  • 0 in reply to Norman Wong
    Intellectual 600 points
    Thanks Norman. I haven't tried the simple SPI setup. I'm going to do that today.
  • 0 in reply to MN
    Guru 26430 points

    All things have been done before. I did a bit of searching. Your SPI code seems to be have been derived from this thread:

    e2e.ti.com/.../170614

    See a post by Steven Ji where he attaches 4670.edma_spi.zip.
    The following reply by xinwei shi verified that it works on a C6678 evm board.

    There are some key differences between Steven's code and your code in your first post.
    - DMA usually has strict alignment requirements of buffers. Steven used #pragmas to align to 8 bytes (I think.). Your code will align to Uint16 or 2 bytes. the DMA controller doesn't like your address, it will generate errors. That said, the doc says there are alignment requirements if SAM oir DAM is 1. I think you have it as 0. It should not matter.
    - Steven seem do some address translation with calls to global_address()

  • 0 in reply to Norman Wong
    Intellectual 600 points

    Thanks so much Norman.  I did change the buffers to be aligned to 8 bytes in .ddrdata section as Steven suggested in that post.  Now I see my data going to SPIDAT0 register, but now it seems that it gets stuck there and the EMR and SER registers suggest that the dma is being missed.  I also get a  BITERRFLG now for some reason. So, I'm guessing that the problem is at the receiving point with ADC and hardware.  I'm looking more into it.

  • 0 in reply to MN
    Guru 26430 points
    In general, SPI masters cannot tell if the slave is there at all. Code should run regardless of the presence of the slave. You might to be careful when polling for Tx and Rx events as the order is not usually predictable. Any loops you have should handle Tx before Rx, Rx before Tx or Tx/Rx simultaneously.

    Are you using Stevens code unmodified? His code does assume a certain order but I assume that order is suitable for your processor, C6678.
  • 0 in reply to Norman Wong
    Intellectual 600 points

    Thanks Norman for all your support.  I guess I got the hang of it now.  Just to update if it would be useful for anyone, one of many problems I had was the STATIC bit disabled in OPT field of param setup and link to NULL which was giving me the SER flag.  Since I wanted to transfer only one word, I had to set the STATIC.  

    Also my SPI setup should have been using CS1 (SCS0FUN1) pin instead of CS0 per evaluation module's manual:

    /* Configure SPI in 4-pin SCS mode */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIPC0=
        CSL_SPI_SPIPC0_SOMIFUN_SPI<<CSL_SPI_SPIPC0_SOMIFUN_SHIFT|
        CSL_SPI_SPIPC0_SIMOFUN_SPI<<CSL_SPI_SPIPC0_SIMOFUN_SHIFT|
        CSL_SPI_SPIPC0_CLKFUN_SPI<<CSL_SPI_SPIPC0_CLKFUN_SHIFT|
        CSL_SPI_SPIPC0_SCS0FUN1_SPI<<CSL_SPI_SPIPC0_SCS0FUN1_SHIFT;

  • 0 in reply to MN
    Guru 26430 points
    That is good news. Thanks for posting your solution. I have seen the same sort of EDMA errors but I ignored them as the transfer itself seemed to work. Now I know.

    On your last post, click on the Verified or Solved button to get that satisfying Green outline and mark on the thread. Gives you a few forum points as well.