Hi,
my application uses a DM647 on a PCI card. Data is captured on DM647s Videoport (8bit raw). The captured data (testcase: 640x480 byte at 72MHz from FPGA) is forwarded over the PCI interface into the PCs memory (while data arrives from the Videoport). In a testcase Videoport 0.A is used:
FPGA.port1 -> 72MHz -> VP0.A -> EDMA -> DDR
DDR -> EDMA -> PCI -> PC
The FPGA generates 480 times 640 bytes of data (+8 hblanks). An A-synchronized EDMA transfer is used to move this from the VP into DDR-memory (FIFO Threshold: 640). A TSK polls the EDMA paRam to know 'how far incoming data has been captured'. If there is already new data (checked once every ms), the new block is forwarded over PCI (using an EDMA transfer into the PCIs address window).
As soon as the EDMA->PCI transfer starts, there are several COVR-Interrupts (Capture FIFO overrun). A FIFO overrun (raw fifo size 2560 byte) occurs at 72MHz after about 35us.
The DDR setup seems to be correct. Copying a 256k block from ISRAM to DDR takes 280µs which results in a transfer rate of about 940MB/s. The EDMA transfer into the PCI address window can be quite big - according to this post (http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/p/52779/186870.aspx#186870) this should be ok.
How do I guarantee that the EDMA transfer DDR->PCI does not block the EDMA VP->DDR transfer (in the testcase "for more than 35us")?
bye,
Thomas
