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TMS320C6678: EMIF16 FPGA interface

Part Number: TMS320C6678


Hello,

I'm looking to use the EMIF16 interface to transfer data in the order of 40 MB from the C6678 to an FPGA. CE0 and CE1 are connected to the FPGA and I want to use CE0 to write data. I was looking through the EMIF-NAND flash example provided with the installation of PDK and I have a couple of questions :

A0CR is setup the following way in the example :

hEmif16Cfg->A0CR = (0 \
| (0 << 31) /* selectStrobe */ \
| (0 << 30) /* extWait (never with NAND) */ \
| (0xf << 26) /* writeSetup 10 ns */ \
| (0x3f << 20) /* writeStrobe 40 ns */ \
| (7 << 17) /* writeHold 10 ns */ \
| (0xf << 13) /* readSetup 10 ns */ \
| (0x3f << 7) /* readStrobe 60 ns */ \
| (7 << 4) /* readHold 10 ns */ \
| (3 << 2) /* turnAround 40 ns */ \
| (0 << 0)); /* asyncSize 8-bit bus */ \

Are the writeSetup, writeStrobe, writeHold and their read equivalents programmable? If so, how do I determine what those values need to be?

Thank you,

Viney

  • Hello!
    In such a situation you have to match DSP's and FPGA's capabilities. The latter is heavily defined by the way you implement FPGA's interface block. I had experience to implement memory mapped device in FPGA. So we had to get in sync with address from DSP, read or write signal and handle incoming/output data. You may get idea about process from www.xilinx.com/.../xapp753.pdf. The document is from dinosaur era, but basic principle is about the same.
  • Hi Viney,
    These numbers were selected based on the timing requirements of the NAND flash used for testing the EMIF. You will have to choose values that are appropriate for the interface you have programmed into the FPGA. Remember that the EMIF does not support synchronous transfers. You will have to calculate your values to allow the FPGA to clock in the data. Be sure to take the timing numbers for the EMIF into account when designing our FPGA interface logic.
    Regards,
    Bill