TDA3: TDA3x Users Guide Demo

Hi, Prasad

Thank you for your reply.

I use TDA3xx_multicore_reset.gel

TDA3xx_multicore_reset.gel

I download this gel file from this URL below:

 

and Let me talk about this gel file setting for Cortex_M4_IPU1_C0.

After M4_IPU1_C0 connection,  I do not know how to use.

Script → IPU Unicache and A-MMU configures → Config_MMU

→ Script → TDA3x Multicore Initialization → TDA3xx_MULTICORE_EnableAllCores

and Every cores connected.

but After this operation, I try to load program, but I got error.

Can you tell me how to set for GEL file?

Best Regards
Hiroyasu

Hi, Prasad

Thank you for your reply.
I already set TDA3xx_cortexM4_startup.gel.
I could load program and run. but I do not see comment in TeraTerm.

and I want to know how to set TDA3xx_multicore_reset.gel.

It is described in Users Manual below:

===============
To install the new GEL versions, you need to extract the zip to
<CCS_INSTALL_DIR>/ccsv6/ccs_base
===============

I extract zip file for gel file.
Can you tell me we need other operation for TDA3xx_multicore_reset.gel?

Best Regards
Hiroyasu

Hello Hiroyasu,

when you load TDA3xx_cortexM4_startup.gel, you would get "misc. module configuration" in scripts menu. Can you run function on target connect under this menu and share output of gel for this function.

Also another issue can be your DDR not configured correctly. In CCS memory browser type address 0x80000000 and check by continuously refreshing if memory is stable.

Hi, Prasad

I think memory is O.K. when I access 0x80000000.
and Is it O.K. to operate for TDA3xx_multicore_reset.gel ?

and I share with output of gel file when I run Script → TDA3x Misk Module configuration.

=======================
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Target Connect Sequence Begins ... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> A device reset occurred <<<---
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG1.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG1.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15x15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15x15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: --->>> All Control module lock registers are UNLOCKED <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> Changing RTI1 reaction type to avoid RTI1 resetting the device after 3 minutes... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> Starting IPU A-MMU configurations... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> IPU A-MMU configuration completed. <<<---
Cortex_M4_IPU1_C0: GEL Output: ------------------------------------------------------------------------------------------
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR and DPLL configuration Based on Package selection pin status(Sysboot[7]) <<<---
Cortex_M4_IPU1_C0: GEL Output: ------------------------------------------------------------------------------------------
Cortex_M4_IPU1_C0: GEL Output: --->>> 15x15 Package Detected(SYSBOOT[7]=0)... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL OPP 0 clock config in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL already locked, now unlocking
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> EVE_VID_DSP DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> EVE_VID_DSP_DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 initialization starts (TI 15x15 EVM)... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL clock config for 532MHz is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL clock config for 532MHz is in DONE!
Cortex_M4_IPU1_C0: GEL Output: Launch full leveling
Cortex_M4_IPU1_C0: GEL Output: Updating slave ratios in PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: as per HW leveling output
Cortex_M4_IPU1_C0: GEL Output: HW leveling is now disabled. Using slave ratios from
Cortex_M4_IPU1_C0: GEL Output: PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 532MHz Initialization is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin All Pad Configuration for Vision Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin GMAC_SW MDIO Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End GMAC_SW MDIO Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin GMAC_SW RGMII0 Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End GMAC_SW RGMII0 Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End All Pad Configuration for RGMII usage on EVM Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End All Pad Configuration for Vision Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Target Connect Sequence DONE !!!!! <<<---
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: For STM based tracing on TI EVMs,
Cortex_M4_IPU1_C0: GEL Output: run 'TDA3x EVM I2C EXPANDER CONTROL -> Enable_Trace_Pins()' function from Scripts menu on M4/CS_DAP_DebugSS
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Target Connect Sequence Begins ... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> A device reset occurred <<<---
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG1.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG1.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15x15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15x15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: --->>> All Control module lock registers are UNLOCKED <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> Changing RTI1 reaction type to avoid RTI1 resetting the device after 3 minutes... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> Starting IPU A-MMU configurations... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> IPU A-MMU configuration completed. <<<---
Cortex_M4_IPU1_C0: GEL Output: ------------------------------------------------------------------------------------------
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR and DPLL configuration Based on Package selection pin status(Sysboot[7]) <<<---
Cortex_M4_IPU1_C0: GEL Output: ------------------------------------------------------------------------------------------
Cortex_M4_IPU1_C0: GEL Output: --->>> 15x15 Package Detected(SYSBOOT[7]=0)... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> CORE DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL OPP 0 clock config in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL already locked, now unlocking
Cortex_M4_IPU1_C0: GEL Output: --->>> PER DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP_GMAC DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> EVE_VID_DSP DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DSP DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> EVE_VID_DSP_DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 initialization starts (TI 15x15 EVM)... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL clock config for 532MHz is in progress...
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL already locked, now unlocking....
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR DPLL clock config for 532MHz is in DONE!
Cortex_M4_IPU1_C0: GEL Output: Launch full leveling
Cortex_M4_IPU1_C0: GEL Output: Updating slave ratios in PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: as per HW leveling output
Cortex_M4_IPU1_C0: GEL Output: HW leveling is now disabled. Using slave ratios from
Cortex_M4_IPU1_C0: GEL Output: PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: --->>> DDR3 532MHz Initialization is DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin All Pad Configuration for Vision Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin GMAC_SW MDIO Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End GMAC_SW MDIO Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Begin GMAC_SW RGMII0 Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End GMAC_SW RGMII0 Pad Configuration <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End All Pad Configuration for RGMII usage on EVM Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx End All Pad Configuration for Vision Platform <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA3xx Target Connect Sequence DONE !!!!! <<<---
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: For STM based tracing on TI EVMs,
Cortex_M4_IPU1_C0: GEL Output: run 'TDA3x EVM I2C EXPANDER CONTROL -> Enable_Trace_Pins()' function from Scripts menu on M4/CS_DAP_DebugSS
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
=======================

Best Regards
Hiroyasu

Hello Hiroyasu,

Gel file output looks correct, though not sure why it is run twice (i believe one is when you connect core and other you ran misc. config manually). After running this, i assume you run "enable all cores" function from multicore gel file.

If with too it is failing-

1. Please halt each core and share the snapshot

2. Please confirm you are checking output on UART3

3. There is below note in VSDK user guide, are you making sure you are following these steps?

IMPORTANT NOTE: Binary for Cortex_M4_IPU1_C0 MUST be loaded before Cortex_M4_IPU1_C1 since IPU1-0 does MMU config for the complete IPU1 system. Other binaries can be loaded in any order

Hi, Prasad

I run enable all cores after misc. config

1. I share with snapshot

First before run

After run amd halt

2.I select UART3

3. I Load Cortex_M4_IPU1_C0 → Cortex_M4_IPU1_C1

and Users Manual says below:

===============
To install the new GEL versions, you need to extract the zip to 
<CCS_INSTALL_DIR>/ccsv6/ccs_base
===============

I share with snapshot.

Is it correct?

Best Regards
Hiroyasu

Hello Hiroyasu,

All steps you following are correct. As seen from second CCS snapshot, IPU1_0 is waiting in IPC attach meaning waiting for some core to come up. 

Why in before running snapshot you are not loading binary on IPU0_1 and EVE? 

Hi,Prasad

I'm sorry IPU1_C1 is my mistake.
Actually I load program for IPU1_C1

but I already vision_sdk_arp32_1_release.xearp32F for EVE.

○vision_sdk_arp32_1_release.xearp32F
C:\VISION_SDK_02_12_01_00\vision_sdk\binaries\tda3xx_evm_bios_all\vision_sdk\bin\tda3xx-evm

Is it correct ?

After I load, EVE run automatically.
and CCS shows "no symbols" when I halt.

Best Regards
Hiroyasu

Hiroyasu,

Some issue with EVE MMU. Normally after loading binary EVE should halt at main like other cores.
When EVE starts running automatically, please check contents of registers 0x6208_1018, 0x6208_101C and 0x6208_1048 from IPU

Share the contents.

Hi, Prasad

I'm sorry. It was late.
I checked these register below.

0x62081018 = 0x00000000
0x6208101C = 0x00000000
0x62081048 = 0x00000180

Best Regards
Hiroyasu

Hiroyasu,

Is this after EVE code is loaded and it is in 'running' state (not halting)?

Hi, Prasad

I got this value after EVE run and halt.

Best Regards
Hiroyasu

Hello Hiroyasu,

Is it possible to share here VSDK multicore gel and your EVE map file?
Or else please mail me both.