Part Number: AM5728
Tool/software: TI-RTOS
Hi,
I am not able to get emac interrupt pacing to work. In drv/emac/src/v4/emac_cpsw.c we see in EMAC_cpdmaOpen:
#ifdef CPSW3G_USE_INTERRUPT_PACING
/* enable Interrupt Pacing Logic in the Wrapper */
EMAC_cpswWrSetRxIntPerSec(cpsw3gCfg->baseConfig.wrpr_base, 0, EMAC_RX_ISR_PER_SEC);
EMAC_cpswWrSetIntPacingEnable(cpsw3gCfg->baseConfig.wrpr_base, CSL_ECTL_INT_CONTROL_INT_PACE_EN_C0_RX);
EMAC_cpswWrSetIntPrescaler(cpsw3gCfg->baseConfig.wrpr_base, 0x370);
#endif
CPSW3G_USE_INTERRUPT_PACING is defined and this code is being called. On investigation I saw a couple of potential problems:
- EMAC_cpswWrSetRxIntPerSec actually passes the EMAC_RX_ISR_PER_SEC value directly to the pacing register, which has units of 'ISRs per MILLIsecond' (NOT second), with a maximum value of 63.
- My understanding is that the emac interface clock is 125MHz, so the int prescaler value should be 500 (0x1F4), NOT 0x370.
I also wrote an equivalent function for Tx interrupt pacing EMAC_cpswWrSetTxIntPerSec and additionally enabled Tx interrupt pacing with:
EMAC_cpswWrSetIntPacingEnable(cpsw3gCfg->baseConfig.wrpr_base, CSL_ECTL_INT_CONTROL_INT_PACE_EN_C0_TX);
However, even having corrected the presumed problems and adding tx interrupt pacing with a value of 8 interrupts per millisecond, I can see from an execution graph that the (tx) interrupt pacing is not working:
The period between the two blue dmtimer interrupts is 125us, and I would expect to see a single EMAC tx interrupt in this period. Instead I can clearly see three EMAC tx interrupts, one for each packet sent (I am sending 24000 packets per second in this test).
I cannot easily test rx interrupt pacing right now, but from the CPU loads I am seeing I get the feeling this is not working either...
Thanks, Kieran.
