Hi,
I have one question regarding "i874" of AM572x Errata.
The description of the errata is the below.
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When TIMER5, TIMER6, TIMER7, or TIMER8 clocks are enabled
(CM_IPU_TIMER5/6/7/8_CLKCTRL[0:1]MODULEMODE=0x2:ENABLE) and the CD-IPU
is in HW_AUTO mode (CM_IPU_CLKSTCTRL[0:1]CLKTRCTRL=0x3:HW_AUTO) the
corresponding TIMER will continue counting, but enabled interrupts will not be
propagated to the destinations (MPU, DSP, etc) in the SoC until the TIMER registers are
accessed from the CPUs (MPU, DSP etc.). This can result in missed timer interrupts.
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From the above description, I think this symptom( the timer interrupt will not be propagated to the destinations(MPU, DSP etc.) is solved if the timer registers are accessed from the CPUs.
What does this mean? If CPU access to timer registers never be happened, the timer interrupt never be propagated to the destination? If CPU access to timer registers are happened, only previous timer interrupt is not be propagated to the destinations?
Please let me know.
I appreciate your quick reply.
Best regards,
Michi
