Hello,
When I setup my EMIF interface to accept wait request signals from the wait request input, it doesn't seem to extend the emif cycle time.
If I look at the EMIF signals on a logic analyzer, the EM_WAIT signal is definitely pulled up by my FPGA when it wants the bus to wait, but the oe_n or we_n signals are still the active for only the set number of clock cycles, may be I'm missing something......
I've got my EMIF setup as follows:
//
//Setup EMIF Wait Configuration to be active high and allow up
// to 16 wait cycles
//
//WP0 = 0x1 << 28
//MEWC = 0x0F << 0
//
WAITCFG_VAL: .word 0x1000000F
/*
* 31 0
*
* 0100 0000 0101 1010 0001 1111 1000 0100
* ---- ---- ---- ---- ---- ---- ---- ----
* ABCC CCDD DDDD EEEF FFFG GGGG GHHH IIJJ
*
* Index Field Hex
* ----- ----- ---
* A SS 0x0
* B EW 0x1
* C W_SETUP 0x0
* D W_STROBE 0x5
* E W_HOLD 0x5
* F R_SETUP 0x0
* G R_STROBE 0x3F
* H R_HOLD 0x0
* I TA 0x1
* J ASIZE 0x0
ACFG4_VAL: .word 0x405A1F84
Thanks