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EMIF EM_WAIT Signal Doesn't Seem to be working

MikeP12806
Intellectual 450 points

Hello,

When I setup my EMIF interface to accept wait request signals from the wait request input, it doesn't seem to extend the emif cycle time.

If I look at the EMIF signals on a logic analyzer, the EM_WAIT signal is definitely pulled up by my FPGA when it wants the bus to wait, but the oe_n or we_n signals are still the active for only the set number of clock cycles, may be I'm missing something......

I've got my EMIF setup as follows:

//
//Setup EMIF Wait Configuration to be active high and allow up
//  to 16 wait cycles
//
//WP0  = 0x1  << 28
//MEWC = 0x0F << 0
//
WAITCFG_VAL:            .word 0x1000000F

 /*
 *    31                                    0
 *
 *    0100 0000 0101 1010 0001 1111 1000 0100
 *    ---- ---- ---- ---- ---- ---- ---- ----
 *    ABCC CCDD DDDD EEEF FFFG GGGG GHHH IIJJ
 *
 *    Index    Field        Hex
 *    -----    -----        ---
 *    A        SS            0x0
 *    B        EW            0x1
 *    C        W_SETUP    0x0
 *    D        W_STROBE    0x5
 *    E        W_HOLD    0x5
 *    F        R_SETUP    0x0
 *    G        R_STROBE    0x3F
 *    H        R_HOLD    0x0
 *    I        TA            0x1
 *    J        ASIZE        0x0

ACFG4_VAL:            .word 0x405A1F84

 

Thanks

  • 0
    TI__Expert 8260 points

    Mike,

    Which part are you talking about?

    Regards, Srirami.

  • 0 in reply to MikeP12806
    TI__Guru*** 125430 points

    What's the value in PINMUX0 at run-time (32-bit register at address 0x01C40000)?

  • 0 in reply to Brad Griffis
    Intellectual 450 points

    Brad,

     

    Here is my PINMUX0 and PINMUX1 values read right before the operation:

    PINMUX0: 0x00000C1F
    PINMUX1: 0x0001000F

  • 0 in reply to MikeP12806
    TI__Guru*** 125430 points

    That confirms that your pinmuxing is correct, i.e. HPIEN=0 and ATAEN=0. 

    Can you please attach a logic analyzer plot of one of these unsuccessful extended waits?  Is this the case all the time?  Is it this way on multiple boards?

    Can you please double-check your schematics to be certain that your FPGA wait signal is connected to the correct ball of the DM6446 (F1)?

    Can you please dump out the following EMIF registers after performing an access where WAIT is asserted:

    • 0x01E00004 AWCCR
    • 0x01E0001C A4CR
    • 0x01E00040 EIRR

    I know that's a bit redundant with your code you showed earlier, but I want to be absolutely certain that the correct values made it all the way to the registers and that they weren't somehow corrupted or something.

  • 0 in reply to Brad Griffis
    Intellectual 450 points

    Brad,

     

    Looks like I found the issue when looking through what you had suggested.  I printed out all of the registers at run-time and found this:

    Before:

    PINMUX0: 0x00000C1F
    PINMUX1: 0x0001000F
    AWCCR: 0xF000008F
    A3CR: 0x003A0284
    A4CR: 0x3FFFFFFC
    EIRR: 0x00000000

     

    After:

    PINMUX0: 0x00000C1F
    PINMUX1: 0x0001000F
    AWCCR: 0xF000008F
    A3CR: 0x003A0284
    A4CR: 0x3FFFFFFC
    EIRR: 0x00000004

     

    I'm tied up to CS4, so A3CR should be the correct configuration register and the EW bit is not set.  I had set it in my startup code, but somewhere along the line it became unset.  All of the other bits are still correct, so I'm not sure why it was unset.  However, if I set it in the run-time code right after I read them out, the wait states start working.

     

    Thanks for your help.

     

    Mike