All,
My customer had started a forum post to help resolve their audio issue on a DM365 product. It looks like this needs some inputs from the codec team, so I have inlcuded the original post link and some additional details below.
Can you please help with this as they are in critical crunch mode to release their product? Thanks!
Original post - http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/p/57589/208408.aspx#208408
Additional details:
Below is the physical connection for the I2S. The signals on the left are connected to an FPGA and the signals on the right are the DM365. The serial audio is in the format of 32 bits left channel followed by 32 bits right channel. The MCBSP_FSR is 32 bits high, during the 32 bit left channel, followed by 32 bits low during the right channel, repeating.
For the first question you provided:
Ø Would it be the audio file on the PC is fixed? When you do the play back you literally “transmit” that audio data to the speaker?
The DM365 encodes the I2S serial audio data and creates a file. This file is then played on a PC using VLC. The file consistently maintains left and right audio when the PC transmits the audio to the speaker. Once a file is created, the audio does not swap channels.
Ø So I am not sure why they think the channel swap issue has something to do with the receive side of the McBSP?
The I2S serial audio is sent from the FPGA, AUD_FPGA_SDAT0, and is RECEIVED by the DM365 on pin E6. It is this path that seems to have the channel swap problem between power-on of the system. The McBSP receive path is configured as slave which encodes the audio using the AAC encoder.
Could you explain the data path of the serial audio data and how the channel assignment is done as the data is read in from MCBSP_DR? What is the EDMA buffer mechanism?
