AM5728: L3 custom errors when starting DSPs

Gerard

Part Number: AM5728
Other Parts Discussed in Thread: BQ40Z60,

I'm seeing different behavior when loading the same DSP firmware image (with the exception of trivial address differences in the resource tables) on DSP1 vs. DSP2.

DSP1

Starting DSP1 results in a single L3 custom error, each and every time:

[ 298.448466] WARNING: CPU: 0 PID: 0 at linux-4.4.32+gitAUTOINC+adde2ca9f8-gadde2ca9f8/drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x258/0x368()
[ 298.465839] 44000000.ocp:L3 Custom Error: MASTER DSP1_MDMA TARGET L4_PER1_P3 (Read): Data Access in User mode during Functional access
[ 298.477976] Modules linked in: virtio_rpmsg_bus cmemk(O) omap_remoteproc remoteproc virtio_ring virtio xhci_plat_hcd xhci_hcd usbcore usb_f_ecm g_ether usb_f_rndis libcomposite u_ether dwc3 extcon_palmas udc_core uio_pdrv_genirq uio phy_omap_usb2 dwc3_omap bridge stp llc xt_tcpudp ipv6 iptable_filter ip_tables x_tables hw_info fpga_config bq40z60_battery mpu9250(C) extcon_usb_gpio extcon rtc_isl1208
[ 298.516573] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G C O 4.4.32-gadde2ca9f8 #1
[ 298.524783] Hardware name: Generic DRA74X (Flattened Device Tree)
[ 298.530902] Backtrace:
[ 298.533378] [<c0013068>] (dump_backtrace) from [<c0013264>] (show_stack+0x18/0x1c)
[ 298.540978] r6:20080193 r5:c0acbb68 r4:00000000 r3:00000000
[ 298.546703] [<c001324c>] (show_stack) from [<c02dea68>] (dump_stack+0x9c/0xb0)
[ 298.553964] [<c02de9cc>] (dump_stack) from [<c00347f4>] (warn_slowpath_common+0x8c/0xbc)
[ 298.562089] r6:c030c984 r5:00000009 r4:c0aadd40 r3:c0aac000
[ 298.567811] [<c0034768>] (warn_slowpath_common) from [<c003485c>] (warn_slowpath_fmt+0x38/0x40)
[ 298.576544] r8:c07fc150 r7:00000002 r6:e0082164 r5:c07fbd2c r4:c07fbe48
[ 298.583319] [<c0034828>] (warn_slowpath_fmt) from [<c030c984>] (l3_interrupt_handler+0x258/0x368)
[ 298.592226] r3:de1fd000 r2:c07fbe48
[ 298.595831] r4:80080003
[ 298.598387] [<c030c72c>] (l3_interrupt_handler) from [<c0079188>] (handle_irq_event_percpu+0x90/0x148)
[ 298.607731] r10:c0af5514 r9:de1f7540 r8:00000017 r7:00000000 r6:00000000 r5:de1f75a0
[ 298.615635] r4:de1fd500
[ 298.618190] [<c00790f8>] (handle_irq_event_percpu) from [<c0079280>] (handle_irq_event+0x40/0x64)
[ 298.627098] r10:c0aac000 r9:c0652a24 r8:de008000 r7:00000001 r6:c0ab3534 r5:de1f75a0
[ 298.635002] r4:de1f7540
[ 298.637558] [<c0079240>] (handle_irq_event) from [<c007c550>] (handle_fasteoi_irq+0xc0/0x194)
[ 298.646118] r6:c0ab3534 r5:de1f75a0 r4:de1f7540 r3:00000000
[ 298.651839] [<c007c490>] (handle_fasteoi_irq) from [<c00787c4>] (generic_handle_irq+0x2c/0x3c)
[ 298.660484] r7:00000001 r6:00000000 r5:00000000 r4:c0aa84ac
[ 298.666204] [<c0078798>] (generic_handle_irq) from [<c0078a9c>] (__handle_domain_irq+0x64/0xbc)
[ 298.674945] [<c0078a38>] (__handle_domain_irq) from [<c0009470>] (gic_handle_irq+0x40/0x7c)
[ 298.683329] r8:fa213000 r7:fa212000 r6:c0aadef0 r5:fa21200c r4:c0aae97c r3:c0aadef0
[ 298.691152] [<c0009430>] (gic_handle_irq) from [<c064c700>] (__irq_svc+0x40/0x74)
[ 298.698667] Exception stack(0xc0aadef0 to 0xc0aadf38)
[ 298.703743] dee0: 00000001 00000000 fe600000 00000000
[ 298.711955] df00: c0aae56c 00000000 00000000 c0aadf60 c0aae5b8 c0652a24 c0aac000 c0aadf4c
[ 298.720170] df20: c0aadf2c c0aadf40 c0027940 c0010568 60080013 ffffffff
[ 298.726810] r8:c0aae5b8 r7:c0aadf24 r6:ffffffff r5:60080013 r4:c0010568 r3:c0027940
[ 298.734635] [<c0010540>] (arch_cpu_idle) from [<c006ed7c>] (default_idle_call+0x28/0x34)
[ 298.742765] [<c006ed54>] (default_idle_call) from [<c006efd8>] (cpu_startup_entry+0x1fc/0x260)
[ 298.751423] [<c006eddc>] (cpu_startup_entry) from [<c064728c>] (rest_init+0x90/0x94)
[ 298.759196] r7:00000000
[ 298.761755] [<c06471fc>] (rest_init) from [<c0891d70>] (start_kernel+0x418/0x424)
[ 298.769268] r4:c0af8050 r3:c0aac000
[ 298.772877] [<c0891958>] (start_kernel) from [<80008090>] (0x80008090)
[ 298.779432] ---[ end trace 05ffeb39f58d2c69 ]---

DSP2:

Starting DSP2 results in endless L3 exception spam - ultimately our board needs to be manually power-cycled to recover.

[ 237.443979] WARNING: CPU: 0 PID: 0 at linux-4.4.32+gitAUTOINC+adde2ca9f8-gadde2ca9f8/drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x258/0x368()
[ 237.461351] 44000000.ocp:L3 Custom Error: MASTER DSP2_DMA TARGET L4_PER3_P3 (Idle): Data Access in User mode during Functional access
[ 237.473400] Modules linked in: rpmsg_proto virtio_rpmsg_bus cmemk(O) omap_remoteproc remoteproc virtio_ring virtio xhci_plat_hcd xhci_hcd usbcore usb_f_ecm g_ether usb_f_rndis libcomposite u_ether dwc3 udc_core uio_pdrv_genirq uio extcon_palmas phy_omap_usb2 dwc3_omap bridge stp llc xt_tcpudp ipv6 iptable_filter ip_tables x_tables hw_info fpga_config bq40z60_battery mpu9250(C) extcon_usb_gpio extcon rtc_isl1208
[ 237.513064] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G WC O 4.4.32-gadde2ca9f8 #1
[ 237.521279] Hardware name: Generic DRA74X (Flattened Device Tree)
[ 237.527398] Backtrace:
[ 237.529875] [<c0013068>] (dump_backtrace) from [<c0013264>] (show_stack+0x18/0x1c)
[ 237.537477] r6:20070193 r5:c0acbb68 r4:00000000 r3:00000000
[ 237.543203] [<c001324c>] (show_stack) from [<c02dea68>] (dump_stack+0x9c/0xb0)
[ 237.550463] [<c02de9cc>] (dump_stack) from [<c00347f4>] (warn_slowpath_common+0x8c/0xbc)
[ 237.558586] r6:c030c984 r5:00000009 r4:c0aadd40 r3:c0aac000
[ 237.564311] [<c0034768>] (warn_slowpath_common) from [<c003485c>] (warn_slowpath_fmt+0x38/0x40)
[ 237.573044] r8:c07fc18c r7:00000000 r6:e0080e64 r5:c07fbd2c r4:c07fbe48
[ 237.579816] [<c0034828>] (warn_slowpath_fmt) from [<c030c984>] (l3_interrupt_handler+0x258/0x368)
[ 237.588724] r3:de1fd000 r2:c07fbe48
[ 237.592330] r4:80080003
[ 237.594887] [<c030c72c>] (l3_interrupt_handler) from [<c0079188>] (handle_irq_event_percpu+0x90/0x148)
[ 237.604232] r10:c0af5514 r9:de1f7540 r8:00000017 r7:00000000 r6:00000000 r5:de1f75a0
[ 237.612137] r4:de1fd500
[ 237.614696] [<c00790f8>] (handle_irq_event_percpu) from [<c0079280>] (handle_irq_event+0x40/0x64)
[ 237.623606] r10:c0aac000 r9:c0652a24 r8:de008000 r7:00000001 r6:c0ab3534 r5:de1f75a0
[ 237.631513] r4:de1f7540
[ 237.634072] [<c0079240>] (handle_irq_event) from [<c007c550>] (handle_fasteoi_irq+0xc0/0x194)
[ 237.642630] r6:c0ab3534 r5:de1f75a0 r4:de1f7540 r3:00000000
[ 237.648356] [<c007c490>] (handle_fasteoi_irq) from [<c00787c4>] (generic_handle_irq+0x2c/0x3c)
[ 237.657001] r7:00000001 r6:00000000 r5:00000000 r4:c0aa84ac
[ 237.662724] [<c0078798>] (generic_handle_irq) from [<c0078a9c>] (__handle_domain_irq+0x64/0xbc)
[ 237.671465] [<c0078a38>] (__handle_domain_irq) from [<c0009470>] (gic_handle_irq+0x40/0x7c)
[ 237.679849] r8:fa213000 r7:fa212000 r6:c0aadef0 r5:fa21200c r4:c0aae97c r3:c0aadef0
[ 237.687678] [<c0009430>] (gic_handle_irq) from [<c064c700>] (__irq_svc+0x40/0x74)
[ 237.695195] Exception stack(0xc0aadef0 to 0xc0aadf38)
[ 237.700271] dee0: 00000001 00000000 fe600000 00000000
[ 237.708487] df00: c0aae56c 00000000 00000000 c0aadf60 c0aae5b8 c0652a24 c0aac000 c0aadf4c
[ 237.716703] df20: c0aadf2c c0aadf40 c0027940 c0010568 60070013 ffffffff
[ 237.723346] r8:c0aae5b8 r7:c0aadf24 r6:ffffffff r5:60070013 r4:c0010568 r3:c0027940
[ 237.731178] [<c0010540>] (arch_cpu_idle) from [<c006ed7c>] (default_idle_call+0x28/0x34)
[ 237.739310] [<c006ed54>] (default_idle_call) from [<c006efd8>] (cpu_startup_entry+0x1fc/0x260)
[ 237.747968] [<c006eddc>] (cpu_startup_entry) from [<c064728c>] (rest_init+0x90/0x94)
[ 237.755741] r7:00000000
[ 237.758300] [<c06471fc>] (rest_init) from [<c0891d70>] (start_kernel+0x418/0x424)
[ 237.765812] r4:c0af8050 r3:c0aac000
[ 237.769424] [<c0891958>] (start_kernel) from [<80008090>] (0x80008090)

Notes:

While DSP1 starting appears to only cause a single L3 custom error, DSP2 starting results in endless errors spamming the ARM.
DSP1
- DSP1's L3 custom error master/initiator seems to always be MDMA
- DSP1's L3 custom error target is generally L4_PER1_P3 or L4_PER3_P3
DSP2
- DSP2's L3 custom error master/initiator seems to always be DMA
- DSP2's L3 custom error target varies (L4_PER#_P#, DMM_P#, etc)

Why am I seeing such different behavior between DSP1 and DSP2 with the same firmware image?

Our firmware image isn't utilizing DMA for anything at this point; why am I seeing the master/initiator show up as MDMA/DMA?

Any help as to where to start looking would be very much appreciated.

Thanks

Processor SDK 03.02.00.05

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The software team have been notified. They will respond here.

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi,

Can you share what command do you use to start each DSP? Also are you using the prebuilt dsp firmware or a custom one?

Also it is a good idea to check your dts, because as I understand you use custom board. See if the dma channels dedicated to the dsp are used by any other module.

Best Regards,
Yordan

0 Yordan Kovachev over 8 years ago in reply to Yordan Kovachev

TI__Guru**** 161600 points

Hi,

Some more thoughts on this.

This error usually come up when trying to access module that is disabled on region that is locked. You should check at which register/address access exactly this error is generating, especially if you use a custom dsp binary. It usually us an erroneous memory address, which the dsp is trying to access.

See this discussion:
e2e.ti.com/.../437761

Also a very strange solution, that I've seen for custom errors is to completely remove the rtc entries from your dts. I've no explanation on this, but I've seen it work in cases of L3 custom errors.

Best Regards,
Yordan

0 Gerard over 8 years ago in reply to Yordan Kovachev

Expert 1290 points

Yordan Kovachev said:

Can you share what command do you use to start each DSP? Also are you using the prebuilt dsp firmware or a custom one?

We start/stop the DSPs dynamically utilizing the bind/unbind nodes (/sys/bus/platform/drivers/omap-rproc/[bind,unbind]). Symlinks are utilized to point the firmware path embedded within the remoteproc driver to the appropriate custom DSP firmware we want to load at that instant.

Yordan Kovachev said:

Also it is a good idea to check your dts, because as I understand you use custom board. See if the dma channels dedicated to the dsp are used by any other module.

I've attached our custom board device tree file which was based on the AM5728 EVM file. We're not explicitly using DMA within our custom firmware images running on the DSPs. Do you see anythingusing dma channels within our device tree file?

Yordan Kovachev said:

This error usually come up when trying to access module that is disabled on region that is locked. You should check at which register/address access exactly this error is generating, especially if you use a custom dsp binary. It usually us an erroneous memory address, which the dsp is trying to access.

Where would I find what register/address is being accessed? The only visibility I have is in the form of these L3 custom errors that pop up in the kernel log on the ARM side. From what we can tell the DSP side keeps running.

Yordan Kovachev said:

Also a very strange solution, that I've seen for custom errors is to completely remove the rtc entries from your dts. I've no explanation on this, but I've seen it work in cases of L3 custom errors.

I'll remove a carry-over rtc reference in the device tree file from the 5728 EVM device tree file we started from but I'm not too optimistic it will make a difference since we see different behavior on DSP1 vs. DSP2.

If you see any other errors/concerns in the attached device tree file I'd be very curious to hear of them.

Thanks

Fullscreen am572x-custom-main.dts.txt Download

/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
    model = "TI AM572x Custom";
    compatible = "ti,am572x-custom", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";

    memory {
        device_type = "memory";
        reg = <0x0 0x80000000 0x0 0x80000000>;
    };

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        /* 0xe000 0000 - 0xe7ff ffff */
        dsp1_cma_pool: dsp1_cma@e0000000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0xe0000000 0x0 0x8000000>;
            reusable;
            status = "okay";
        };
       
        /* 0xe800 0000 - 0xefff ffff */
        dsp2_cma_pool: dsp2_cma@e8000000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0xe8000000 0x0 0x8000000>;
            reusable;
            status = "okay";
        };
        
        ipu1_cma_pool: ipu1_cma@df000000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0xdf000000 0x0 0x800000>;
            reusable;
            status = "okay";
        };
        
        ipu2_cma_pool: ipu2_cma@df800000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0xdf800000 0x0 0x800000>;
            reusable;
            status = "okay";
        };
    };

    vdd_3v3: fixedregulator-vdd_3v3 {
        compatible = "regulator-fixed";
        regulator-name = "vdd_3v3";
        vin-supply = <&regen1>;
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
    };

    aic_dvdd: fixedregulator-aic_dvdd {
        compatible = "regulator-fixed";
        regulator-name = "aic_dvdd_fixed";
        vin-supply = <&vdd_3v3>;
        regulator-min-microvolt = <1800000>;
        regulator-max-microvolt = <1800000>;
    };

    vtt_fixed: fixedregulator-vtt {
        /* TPS51200 */
        compatible = "regulator-fixed";
        regulator-name = "vtt_fixed";
        vin-supply = <&smps3_reg>;
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        regulator-always-on;
        regulator-boot-on;
        enable-active-high;
        gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>;
    };

    hw_info {
        compatible = "hw_info";
        check-hw-type;
        type-gpios    = <&gpio3  0 GPIO_ACTIVE_HIGH>,   /* VERSION_0 */
                        <&gpio3  1 GPIO_ACTIVE_HIGH>,   /* VERSION_1 */
                        <&gpio3  2 GPIO_ACTIVE_HIGH>,   /* VERSION_2 */
                        <&gpio3  3 GPIO_ACTIVE_HIGH>;   /* VERSION_3 */

        check-hw-version;
        version-gpios = <&gpio5  4 GPIO_ACTIVE_HIGH>,   /* VERSION_4 */
                        <&gpio5  5 GPIO_ACTIVE_HIGH>,   /* VERSION_5 */
                        <&gpio5  6 GPIO_ACTIVE_HIGH>,   /* VERSION_6 */
                        <&gpio5  7 GPIO_ACTIVE_HIGH>,   /* VERSION_7 */
                        <&gpio5  8 GPIO_ACTIVE_HIGH>,   /* VERSION_8 */
                        <&gpio5  9 GPIO_ACTIVE_HIGH>,   /* VERSION_9 */
                        <&gpio5  10 GPIO_ACTIVE_HIGH>,  /* VERSION_10 */
                        <&gpio5  11 GPIO_ACTIVE_HIGH>;  /* VERSION_11 */
    };

    contact_closure {
        compatible = "contact-closure";

        REAL_GPIOS {
            trigger_in_n-gpios =  <&gpio3  4 GPIO_ACTIVE_LOW>,   /* TRIGGER_IN_1_N */
                                  <&gpio3  5 GPIO_ACTIVE_LOW>,   /* TRIGGER_IN_2_N */
                                  <&gpio3  6 GPIO_ACTIVE_LOW>,   /* TRIGGER_IN_3_N */
                                  <&gpio3  7 GPIO_ACTIVE_LOW>;   /* TRIGGER_IN_4_N */
        
            trigger_latch-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>,  /* TRIGGER_LATCH_1 */
                                  <&gpio3 14 GPIO_ACTIVE_HIGH>,  /* TRIGGER_LATCH_2 */
                                  <&gpio3 15 GPIO_ACTIVE_HIGH>,  /* TRIGGER_LATCH_3 */
                                  <&gpio3 16 GPIO_ACTIVE_HIGH>;  /* TRIGGER_LATCH_4 */

            clear_latches-gpios = <&gpio3  8 GPIO_ACTIVE_HIGH>;
            
            trigger_out-gpios =   <&gpio3  9 GPIO_ACTIVE_HIGH>,  /* TRIGGER_OUT_1 */
                                  <&gpio3 10 GPIO_ACTIVE_HIGH>;  /* TRIGGER_OUT_2 */
        };
    };
 
    extcon_usb1: extcon_usb1 {
        compatible = "linux,extcon-usb-gpio";
        id-gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
    };
    
    /* Needs CONFIG_POWER_RESET_GPIO=y */
    gpio-poweroff {
        compatible = "gpio-poweroff";
        gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
    };
    
    fpga_config {
        status = "okay";
        compatible = "fpga_config";
    };
};

&dpll_dsp_ck {
    assigned-clock-rates = <750000000>;
};

&dpll_dsp_m2_ck {
    assigned-clock-rates = <750000000>;
};

&dpll_dsp_m3x2_ck {
    assigned-clock-rates = <500000000>;
};

&dpll_iva_ck {
    assigned-clock-rates = <1064000000>;
};

&dpll_iva_m2_ck {
    assigned-clock-rates = <532000000>;
};

&dra7_pmx_core {
    clkout_pins_up: clkout_pins_up {
        pinctrl-single,pins = <
            0x290   (PULL_DIS | MUX_MODE9)              /* gpio6_16.clkout1 */
            0x294   (PULL_DIS | MUX_MODE9)              /* xref_clk0.clkout2 */
        >;
    };

    gpmc_pins_up: gpmc_pins_up {
        pinctrl-single,pins = <
            0x044   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)               /* gpmc_a1.gpmc_a1 */
            0x068   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE12)               /* gpmc_a10.gpmc_a10 */
            0x06C   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)               /* gpmc_a11.gpmc_a11 */
            0x048   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)               /* gpmc_a2.gpmc_a2 */
            0x04C   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE10)               /* gpmc_a3.gpmc_a3 */
            0x050   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE10)               /* gpmc_a4.gpmc_a4 */
            0x054   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)               /* gpmc_a5.gpmc_a5 */
            0x058   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)               /* gpmc_a6.gpmc_a6 */
            0x05C   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)               /* gpmc_a7.gpmc_a7 */
            0x060   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE12)               /* gpmc_a8.gpmc_a8 */
            0x064   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE12)               /* gpmc_a9.gpmc_a9 */
            0x000   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad0.gpmc_ad0 */
            0x004   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad1.gpmc_ad1 */
            0x028   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad10.gpmc_ad10 */
            0x02C   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad11.gpmc_ad11 */
            0x030   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad12.gpmc_ad12 */
            0x034   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad13.gpmc_ad13 */
            0x038   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad14.gpmc_ad14 */
            0x03C   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad15.gpmc_ad15 */
            0x008   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad2.gpmc_ad2 */
            0x00C   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad3.gpmc_ad3 */
            0x010   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad4.gpmc_ad4 */
            0x014   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad5.gpmc_ad5 */
            0x018   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad6.gpmc_ad6 */
            0x01C   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad7.gpmc_ad7 */
            0x020   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad8.gpmc_ad8 */
            0x024   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11)    /* gpmc_ad9.gpmc_ad9 */
            0x0C0   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE12)    /* gpmc_clk.gpmc_clk */
            0x0B8   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE12)               /* gpmc_cs2.gpmc_cs2 */
            0x0BC   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE10)               /* gpmc_cs3.gpmc_cs3 */
            0x0D0   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11 | MUX_MODE1)   /* gpmc_ben0.gpmc_cs4 */
            0x0D4   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE11 | MUX_MODE1)   /* gpmc_ben1.gpmc_cs5 */
            0x0C8   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE14)               /* gpmc_oen_ren.gpmc_oen_ren */
            0x0D8   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE14)    /* gpmc_wait0.gpmc_wait0 */
            0x0C4   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE13 | MUX_MODE3)    /* gpmc_advn_ale.gpmc_wait1 */
            0x0CC   (PULL_DIS | MODE_SELECT | MUX_VIRTUAL_MODE14)               /* gpmc_wen.gpmc_wen */
        >;
    };

    spi1_pins_up: spi1_pins_up {
        pinctrl-single,pins = <
            0x3B0   (PULL_DIS)                          /* spi1_cs0.spi1_cs0 */
            0x3AC   (PULL_DIS)                          /* spi1_d0.spi1_d0 */
            0x3A8   (INPUT_EN | PULL_DIS)               /* spi1_d1.spi1_d1 */
            0x3A4   (INPUT_EN | PULL_DIS)               /* spi1_sclk.spi1_sclk */
        >;
    };

    spi2_pins_up: spi2_pins_up {
        pinctrl-single,pins = <
            0x3CC   (PULL_DIS)                          /* spi2_cs0.spi2_cs0 */
            0x3C8   (PULL_DIS)                          /* spi2_d0.spi2_d0 */
            0x3C4   (INPUT_EN | PULL_DIS)               /* spi2_d1.spi2_d1 */
            0x3C0   (INPUT_EN | PULL_DIS)               /* spi2_sclk.spi2_sclk */
        >;
    };

    clkout3_pins_default: clkout3_pins_default {
        pinctrl-single,pins = <
            0x2A0   (MUX_MODE9)                         /* xref_clk3.clkout3 */
        >;
    };

    dcan1_pins_default: dcan1_pins_default {
        pinctrl-single,pins = <
            0x3D4   (INPUT_EN | PULL_UP)                /* dcan1_rx.dcan1_rx */
            0x3D0   (PULL_UP)                           /* dcan1_tx.dcan1_tx */
        >;
    };

    emu_pins_default: emu_pins_default {
        pinctrl-single,pins = <
            0x448   (INPUT_EN | PULL_DIS)               /* emu0.emu0 */
            0x44C   (INPUT_EN | PULL_DIS)               /* emu1.emu1 */
        >;
    };

    gpio1_pins_default: gpio1_pins_default {
        pinctrl-single,pins = <
            0x010   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad4.gpio1_10 */
            0x014   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad5.gpio1_11 */
            0x018   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad6.gpio1_12 */
            0x01C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad7.gpio1_13 */
            0x3F8   (PULL_DIS | MUX_MODE14)             /* uart2_ctsn.gpio1_16 */
            0x3FC   (PULL_DIS | MUX_MODE14)             /* uart2_rtsn.gpio1_17 */
            0x030   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad12.gpio1_18 */
            0x034   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad13.gpio1_19 */
            0x038   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad14.gpio1_20 */
            0x03C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad15.gpio1_21 */
            0x394   (PULL_DIS | MUX_MODE14)             /* mmc3_dat4.gpio1_22 */
            0x398   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* mmc3_dat5.gpio1_23 */
            0x39C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* mmc3_dat6.gpio1_24 */
            0x3A0   (PULL_DIS | MUX_MODE14)             /* mmc3_dat7.gpio1_25 */
            0x050   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a4.gpio1_26 */
            0x054   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a5.gpio1_27 */
            0x058   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a6.gpio1_28 */
            0x05C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a7.gpio1_29 */
            0x060   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a8.gpio1_30 */
            0x064   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a9.gpio1_31 */
            0x314   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* mcasp2_axr4.gpio1_4 */
            0x000   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad0.gpio1_6 */
            0x004   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad1.gpio1_7 */
            0x008   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad2.gpio1_8 */
            0x00C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad3.gpio1_9 */
        >;
    };
            
    gpio2_pins_default: gpio2_pins_default {
        pinctrl-single,pins = <
            0x068   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a10.gpio2_0 */
            0x06C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a11.gpio2_1 */
            0x0B4   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_cs0.gpio2_19 */
            0x0B8   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_cs2.gpio2_20 */
            0x0BC   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_cs3.gpio2_21 */
            0x0C0   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_clk.gpio2_22 */
            0x0C4   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_advn_ale.gpio2_23 */
            0x0C8   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_oen_ren.gpio2_24 */
            0x0CC   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_wen.gpio2_25 */
            0x0D0   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ben0.gpio2_26 */
            0x0D4   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ben1.gpio2_27 */
            0x0D8   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_wait0.gpio2_28 */
            0x0DC   (INPUT_EN | PULL_UP  | MUX_MODE14)  /* vin1a_clk0.gpio2_30 */
            0x0E0   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1b_clk1.gpio2_31 */
        >;
    };

    gpio3_pins_default: gpio3_pins_default {
        pinctrl-single,pins = <
            0x0E4   (INPUT_EN | PULL_UP | MUX_MODE14)   /* vin1a_de0.gpio3_0 */
            0x0E8   (INPUT_EN | PULL_UP | MUX_MODE14)   /* vin1a_fld0.gpio3_1 */
            0x10C   (PULL_DIS | MUX_MODE14)             /* vin1a_d6.gpio3_10 */
            0x118   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d9.gpio3_13 */
            0x11C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d10.gpio3_14 */
            0x120   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d11.gpio3_15 */
            0x124   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d12.gpio3_16 */
            0x128   (PULL_DIS | MUX_MODE14)             /* vin1a_d13.gpio3_17 */
            0x12C   (PULL_DIS | MUX_MODE14)             /* vin1a_d14.gpio3_18 */
            0x130   (PULL_DIS | MUX_MODE14)             /* vin1a_d15.gpio3_19 */
            0x0EC   (INPUT_EN | PULL_UP | MUX_MODE14)   /* vin1a_hsync0.gpio3_2 */
            0x134   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d16.gpio3_20 */
            0x138   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d17.gpio3_21 */
            0x140   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d19.gpio3_23 */
            0x144   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d20.gpio3_24 */
            0x148   (PULL_DIS | MUX_MODE14)             /* vin1a_d21.gpio3_25 */
            0x14C   (PULL_DIS | MUX_MODE14)             /* vin1a_d22.gpio3_26 */
            0x150   (PULL_DIS | MUX_MODE14)             /* vin1a_d23.gpio3_27 */
            0x154   (PULL_DIS | MUX_MODE14)             /* vin2a_clk0.gpio3_28 */
            0x158   (PULL_DIS | MUX_MODE14)             /* vin2a_de0.gpio3_29 */
            0x0F0   (INPUT_EN | PULL_UP | MUX_MODE14)   /* vin1a_vsync0.gpio3_3 */
            0x15C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin2a_fld0.gpio3_30 */
            0x160   (PULL_DIS | MUX_MODE14)             /* vin2a_hsync0.gpio3_31 */
            0x0F4   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d0.gpio3_4 */
            0x0F8   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d1.gpio3_5 */
            0x0FC   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d2.gpio3_6 */
            0x100   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin1a_d3.gpio3_7 */
            0x104   (PULL_DIS | MUX_MODE14)             /* vin1a_d4.gpio3_8 */
            0x108   (PULL_DIS | MUX_MODE14)             /* vin1a_d5.gpio3_9 */
        >;
    };

    gpio4_pins_default: gpio4_pins_default {
        pinctrl-single,pins = <
            0x164   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin2a_vsync0.gpio4_0 */
            0x168   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin2a_d0.gpio4_1 */
            0x18C   (PULL_DIS | MUX_MODE14)             /* vin2a_d9.gpio4_10 */
            0x190   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin2a_d10.gpio4_11 */
            0x2E0   (PULL_DIS | MUX_MODE14)             /* mcasp1_axr11.gpio4_17 */
            0x2E4   (PULL_DIS | MUX_MODE14)             /* mcasp1_axr12.gpio4_18 */
            0x1C8   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_clk.gpio4_19 */
            0x16C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin2a_d1.gpio4_2 */
            0x170   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin2a_d2.gpio4_3 */
            0x174   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vin2a_d3.gpio4_4 */
            0x178   (PULL_DIS | MUX_MODE14)             /* vin2a_d4.gpio4_5 */
            0x17C   (PULL_DIS | MUX_MODE14)             /* vin2a_d5.gpio4_6 */
            0x180   (PULL_DIS | MUX_MODE14)             /* vin2a_d6.gpio4_7 */
            0x184   (PULL_DIS | MUX_MODE14)             /* vin2a_d7.gpio4_8 */
            0x188   (PULL_DIS | MUX_MODE14)             /* vin2a_d8.gpio4_9 */
        >;
    };

    gpio5_pins_default: gpio5_pins_default {
        pinctrl-single,pins = <
            0x2D4   (INPUT_EN | PULL_UP | MUX_MODE14)   /* mcasp1_axr8.gpio5_10 */
            0x2D8   (INPUT_EN | PULL_UP | MUX_MODE14)   /* mcasp1_axr9.gpio5_11 */
            0x2DC   (PULL_DIS | MUX_MODE14)             /* mcasp1_axr10.gpio5_12 */
            0x324   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* mcasp3_aclkx.gpio5_13 */
            0x250   (PULL_DIS | MUX_MODE14)             /* rgmii0_txc.gpio5_20 */
            0x2BC   (INPUT_EN | PULL_UP | MUX_MODE14)   /* mcasp1_axr2.gpio5_4 */
            0x2C0   (INPUT_EN | PULL_UP | MUX_MODE14)   /* mcasp1_axr3.gpio5_5 */
            0x2C4   (INPUT_EN | PULL_UP | MUX_MODE14)   /* mcasp1_axr4.gpio5_6 */
            0x2C8   (INPUT_EN | PULL_UP | MUX_MODE14)   /* mcasp1_axr5.gpio5_7 */
            0x2CC   (INPUT_EN | PULL_UP | MUX_MODE14)   /* mcasp1_axr6.gpio5_8 */
            0x2D0   (INPUT_EN | PULL_UP | MUX_MODE14)   /* mcasp1_axr7.gpio5_9 */
        >;
    };

    gpio6_pins_default: gpio6_pins_default {
        pinctrl-single,pins = <
            0x378   (INPUT_EN | PULL_DIS)               /* gpio6_11.gpio6_11 */
            0x28C   (INPUT_EN)                          /* gpio6_15.gpio6_15 */
            0x290   (INPUT_EN)                          /* gpio6_16.gpio6_16 */
            0x294   (INPUT_EN | MUX_MODE14)             /* xref_clk0.gpio6_17 */
            0x298   (PULL_DIS | MUX_MODE14)             /* xref_clk1.gpio6_18 */
            0x29C   (PULL_DIS | MUX_MODE14)             /* xref_clk2.gpio6_19 */
            0x370   (INPUT_EN | MUX_MODE14)             /* mmc1_sdwp.gpio6_28 */
            0x2E8   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* mcasp1_axr13.gpio6_4 */
            0x2EC   (INPUT_EN | MUX_MODE14)             /* mcasp1_axr14.gpio6_5 */
            0x2F0   (INPUT_EN | MUX_MODE14)             /* mcasp1_axr15.gpio6_6 */
            0x318   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* mcasp2_axr5.gpio6_7 */
            0x30C   (INPUT_EN | MUX_MODE14)             /* mcasp2_axr2.gpio6_8 */
            0x310   (INPUT_EN | MUX_MODE14)             /* mcasp2_axr3.gpio6_9 */
        >;
    };

    gpio7_pins_default: gpio7_pins_default {
        pinctrl-single,pins = <
            0x3B0   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* spi1_cs0.gpio7_10 */
            0x3C0   (INPUT_EN | MUX_MODE14)             /* spi2_sclk.gpio7_14 */
            0x3C4   (INPUT_EN | MUX_MODE14)             /* spi2_d1.gpio7_15 */
            0x3C8   (INPUT_EN | MUX_MODE14)             /* spi2_d0.gpio7_16 */
            0x3CC   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* spi2_cs0.gpio7_17 */
            0x020   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad8.gpio7_18 */
            0x024   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad9.gpio7_19 */
            0x028   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad10.gpio7_28 */
            0x02C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_ad11.gpio7_29 */
            0x040   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a0.gpio7_3 */
            0x044   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a1.gpio7_4 */
            0x048   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a2.gpio7_5 */
            0x04C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* gpmc_a3.gpio7_6 */
            0x3A4   (INPUT_EN | MUX_MODE14)             /* spi1_sclk.gpio7_7 */
            0x3A8   (INPUT_EN | MUX_MODE14)             /* spi1_d1.gpio7_8 */
            0x3AC   (INPUT_EN | MUX_MODE14)             /* spi1_d0.gpio7_9 */
        >;
    };

    gpio8_pins_default: gpio8_pins_default {
        pinctrl-single,pins = <
            0x1DC   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d0.gpio8_0 */
            0x1E0   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d1.gpio8_1 */
            0x204   (INPUT_EN | MUX_MODE14)             /* vout1_d10.gpio8_10 */
            0x208   (PULL_DIS | MUX_MODE14)             /* vout1_d11.gpio8_11 */
            0x20C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d12.gpio8_12 */
            0x210   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d13.gpio8_13 */
            0x214   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d14.gpio8_14 */
            0x218   (PULL_DIS | MUX_MODE14)             /* vout1_d15.gpio8_15 */
            0x21C   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d16.gpio8_16 */
            0x220   (PULL_DIS | MUX_MODE14)             /* vout1_d17.gpio8_17 */
            0x228   (INPUT_EN | MUX_MODE14)             /* vout1_d19.gpio8_19 */
            0x1E4   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d2.gpio8_2 */
            0x22C   (INPUT_EN | MUX_MODE14)             /* vout1_d20.gpio8_20 */
            0x230   (INPUT_EN | MUX_MODE14)             /* vout1_d21.gpio8_21 */
            0x234   (INPUT_EN | MUX_MODE14)             /* vout1_d22.gpio8_22 */
            0x238   (PULL_DIS | MUX_MODE14)             /* vout1_d23.gpio8_23 */
            0x1E8   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d3.gpio8_3 */
            0x1EC   (INPUT_EN | PULL_DIS | MUX_MODE14)  /* vout1_d4.gpio8_4 */
            0x1F0   (PULL_DIS | MUX_MODE14)             /* vout1_d5.gpio8_5 */
            0x1F8   (INPUT_EN | MUX_MODE14)             /* vout1_d7.gpio8_7 */
            0x1FC   (INPUT_EN | MUX_MODE14)             /* vout1_d8.gpio8_8 */
            0x200   (INPUT_EN | MUX_MODE14)             /* vout1_d9.gpio8_9 */
        >;
    };

    i2c1_pins_default: i2c1_pins_default {
        pinctrl-single,pins = <
            0x400   (INPUT_EN | PULL_DIS)                /* i2c1_sda.i2c1_sda, Different from PinMux Tool */
            0x404   (INPUT_EN | PULL_DIS)                /* i2c1_scl.i2c1_scl */
        >;
    };

    i2c2_pins_default: i2c2_pins_default {
        pinctrl-single,pins = <
            0x408   (INPUT_EN | PULL_DIS)               /* i2c2_sda.i2c2_sda */
            0x40C   (INPUT_EN | PULL_DIS)               /* i2c2_scl.i2c2_scl */
        >;
    };

    i2c5_pins_default: i2c5_pins_default {
        pinctrl-single,pins = <
            0x2B4   (INPUT_EN | PULL_UP | MUX_MODE10)   /* mcasp1_axr0.i2c5_sda */
            0x2B8   (PULL_UP | MUX_MODE10)              /* mcasp1_axr1.i2c5_scl */
        >;
    };

    mdio_pins_default: mdio_pins_default {
        pinctrl-single,pins = <
            0x23C   (INPUT_EN | PULL_DIS)               /* mdio_mclk.mdio_mclk */
            0x240   (INPUT_EN | PULL_DIS)               /* mdio_d.mdio_d */
        >;
    };

    mmc1_pins_default: mmc1_pins_default {
        pinctrl-single,pins = <     
            0x354   (PULL_UP)                           /* mmc1_clk.mmc1_clk */
            0x358   (INPUT_EN | PULL_UP)                /* mmc1_cmd.mmc1_cmd */
            0x35C   (INPUT_EN | PULL_UP)                /* mmc1_dat0.mmc1_dat0 */
            0x360   (INPUT_EN | PULL_UP)                /* mmc1_dat1.mmc1_dat1 */
            0x364   (INPUT_EN | PULL_UP)                /* mmc1_dat2.mmc1_dat2 */
            0x368   (INPUT_EN | PULL_UP)                /* mmc1_dat3.mmc1_dat3 */
            0x36C   (INPUT_EN | PULL_UP)                /* mmc1_sdcd.mmc1_sdcd */
            >;
    };
    mmc1_pins_hs: mmc1_pins_hs {
        pinctrl-single,pins = <
            0x354   (PULL_UP)                           /* mmc1_clk.mmc1_clk */
            0x358   (INPUT_EN | PULL_UP)                /* mmc1_cmd.mmc1_cmd */
            0x35C   (INPUT_EN | PULL_UP)                /* mmc1_dat0.mmc1_dat0 */
            0x360   (INPUT_EN | PULL_UP)                /* mmc1_dat1.mmc1_dat1 */
            0x364   (INPUT_EN | PULL_UP)                /* mmc1_dat2.mmc1_dat2 */
            0x368   (INPUT_EN | PULL_UP)                /* mmc1_dat3.mmc1_dat3 */
            0x36C   (INPUT_EN | PULL_UP)                /* mmc1_sdcd.mmc1_sdcd */
        >;
    };


    mmc2_pins_default: mmc2_pins_default {
        pinctrl-single,pins = <
            0x09C   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a23.mmc2_clk */
            0x0B0   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_cs1.mmc2_cmd */
            0x0A0   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a24.mmc2_dat0 */
            0x0A4   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a25.mmc2_dat1 */
            0x0A8   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a26.mmc2_dat2 */
            0x0AC   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a27.mmc2_dat3 */
            0x08C   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a19.mmc2_dat4 */
            0x090   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a20.mmc2_dat5 */
            0x094   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a21.mmc2_dat6 */
            0x098   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a22.mmc2_dat7 */
        >;
    };
    mmc2_pins_hs: mmc2_pins_hs {
        pinctrl-single,pins = <
            0x09C   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a23.mmc2_clk */
            0x0B0   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_cs1.mmc2_cmd */
            0x0A0   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a24.mmc2_dat0 */
            0x0A4   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a25.mmc2_dat1 */
            0x0A8   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a26.mmc2_dat2 */
            0x0AC   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a27.mmc2_dat3 */
            0x08C   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a19.mmc2_dat4 */
            0x090   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a20.mmc2_dat5 */
            0x094   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a21.mmc2_dat6 */
            0x098   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a22.mmc2_dat7 */
        >;
    };
    mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v {
        pinctrl-single,pins = <
            0x09C   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a23.mmc2_clk */
            0x0B0   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_cs1.mmc2_cmd */
            0x0A0   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a24.mmc2_dat0 */
            0x0A4   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a25.mmc2_dat1 */
            0x0A8   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a26.mmc2_dat2 */
            0x0AC   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a27.mmc2_dat3 */
            0x08C   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a19.mmc2_dat4 */
            0x090   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a20.mmc2_dat5 */
            0x094   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a21.mmc2_dat6 */
            0x098   (INPUT_EN | PULL_UP | MUX_MODE1)    /* gpmc_a22.mmc2_dat7 */
        >;
    };

    nmin_pins_default: nmin_pins_default {
        pinctrl-single,pins = <
            0x460   (INPUT_EN | PULL_DIS)               /* nmin_dsp.nmin_dsp */
        >;
    };

    onreset_pins_default: onreset_pins_default {
        pinctrl-single,pins = <
            0x428   (INPUT_EN | PULL_DIS)               /* on_off.on_off */
            0x45C   (INPUT_EN | PULL_DIS)               /* resetn.resetn */
        >;
    };

    rgmii1_pins_default: rgmii1_pins_default {
        pinctrl-single,pins = <
            0x1B0   (INPUT_EN | MODE_SELECT |MUX_MODE3)             /* vin2a_d18.rgmii1_rxc */
            0x1B4   (INPUT_EN | MODE_SELECT |MUX_MODE3)             /* vin2a_d19.rgmii1_rxctl */
            0x1C4   (INPUT_EN | PULL_UP | MODE_SELECT | MUX_MODE3)  /* vin2a_d23.rgmii1_rxd0 */
            0x1C0   (INPUT_EN | PULL_UP | MODE_SELECT | MUX_MODE3)  /* vin2a_d22.rgmii1_rxd1 */
            0x1BC   (INPUT_EN | PULL_UP | MODE_SELECT | MUX_MODE3)  /* vin2a_d21.rgmii1_rxd2 */
            0x1B8   (INPUT_EN | PULL_UP | MODE_SELECT | MUX_MODE3)  /* vin2a_d20.rgmii1_rxd3 */
            0x198   (MODE_SELECT | MUX_MODE3)                       /* vin2a_d12.rgmii1_txc */
            0x19C   (MODE_SELECT | MUX_MODE3)                       /* vin2a_d13.rgmii1_txctl */
            0x1AC   (MODE_SELECT | MUX_MODE3)                       /* vin2a_d17.rgmii1_txd0 */
            0x1A8   (MODE_SELECT | MUX_MODE3)                       /* vin2a_d16.rgmii1_txd1 */
            0x1A4   (MODE_SELECT | MUX_MODE3)                       /* vin2a_d15.rgmii1_txd2 */
            0x1A0   (MODE_SELECT | MUX_MODE3)                       /* vin2a_d14.rgmii1_txd3 */
        >;
    };

    rmii_pins_default: rmii_pins_default {
        pinctrl-single,pins = <
            0x244   (INPUT_EN | PULL_DIS | MODE_SELECT)             /* RMII_MHZ_50_CLK.RMII_MHZ_50_CLK */
        >;
    };

    rgmii0_pins_default: rgmii0_pins_default {
        pinctrl-single,pins = <
            0x258   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_MODE1) /* rgmii0_txd3.rmii0_crs */
            0x264   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_MODE1) /* rgmii0_txd0.rmii0_rxd0 */
            0x260   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_MODE1) /* rgmii0_txd1.rmii0_rxd1 */
            0x25C   (INPUT_EN | PULL_DIS | MODE_SELECT | MUX_MODE1) /* rgmii0_txd2.rmii0_rxer */
            0x27C   (PULL_DIS | MUX_MODE1)                          /* rgmii0_rxd0.rmii0_txd0 */
            0x278   (PULL_DIS | MUX_MODE1)                          /* rgmii0_rxd1.rmii0_txd1 */
            0x274   (PULL_DIS | MUX_MODE1)                          /* rgmii0_rxd2.rmii0_txen */
        >;
    };

    /* TODO - Remove these per TI's suggestion - they are a carry over from copy/pasting the AM5728 EVM device tree as a starting point */
    rtc_misc_pins_default: rtc_misc_pins_default {
        pinctrl-single,pins = <
            0x464   (PULL_DIS)                  /* rstoutn.rstoutn */
            0x42C   (INPUT_EN | PULL_DIS)       /* rtc_porz.rtc_porz */
            0x444   (PULL_DIS)                  /* rtck.rtck */
            0x43C   (INPUT_EN | PULL_DIS)       /* tclk.tclk */
            0x434   (INPUT_EN | PULL_DIS)       /* tdi.tdi */
            0x438   (PULL_DIS)                  /* tdo.tdo */
            0x430   (INPUT_EN | PULL_DIS)       /* tms.tms */
            0x440   (INPUT_EN | PULL_DIS)       /* trstn.trstn */
        >;
    };

    uart1_pins_default: uart1_pins_default {
        pinctrl-single,pins = <
            0x3E0   (INPUT_EN | PULL_DIS)   /* uart1_rxd.uart1_rxd */
            0x3E4   (PULL_DIS)              /* uart1_txd.uart1_txd */
        >;
    };

    uart3_pins_default: uart3_pins_default {
        pinctrl-single,pins = <
            0x248   (INPUT_EN | PULL_DIS)   /* uart3_rxd.uart3_rxd */
            0x24C   (PULL_DIS)              /* uart3_txd.uart3_txd */
        >;
    };

    uart5_pins_default: uart5_pins_default {
        pinctrl-single,pins = <
            0x32C   (INPUT_EN | PULL_UP | MUX_MODE4)    /* mcasp3_axr0.uart5_rxd */
            0x330   (PULL_DIS | MUX_MODE4)              /* mcasp3_axr1.uart5_txd */
        >;
    };

    usb1_pins_default: usb1_pins_default {
        pinctrl-single,pins = <
            0x280   (PULL_DIS)              /* usb1_drvvbus.usb1_drvvbus */
        >;
    };

    wakeup_pins_default: wakeup_pins_default {
        pinctrl-single,pins = <
            0x418   (INPUT_EN | PULL_DIS)   /* Wakeup0.Wakeup0 */
            0x41C   (INPUT_EN | PULL_DIS)   /* Wakeup1.Wakeup1 */
            0x420   (INPUT_EN | PULL_DIS)   /* Wakeup2.Wakeup2 */
            0x424   (INPUT_EN | PULL_DIS)   /* Wakeup3.Wakeup3 */
        >;
    };
};

&i2c1 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <
                 &i2c1_pins_default 
                >;
    clock-frequency = <400000>;

    /* TPS659037 6ZWST */
    tps659038: tps659038@58 {
        compatible = "ti,tps659038";
        reg = <0x58>;

        #interrupt-cells = <2>;
        interrupt-controller;

        ti,system-power-controller;
        
        ti,mux-pad1 = <8>;
        ti,mux-pad2 = <0x20>;

        tps659038_pmic {
            compatible = "ti,tps659038-pmic";

            regulators {
                smps12_reg: smps12 {
                    /* VDD_MPU */
                    regulator-name = "smps12";
                    regulator-min-microvolt = < 600000>;
                    regulator-max-microvolt = <1250000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                smps3_reg: smps3 {
                    /* VDD_DDR */
                    regulator-name = "smps3";
                    regulator-min-microvolt = <1350000>;
                    regulator-max-microvolt = <1350000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                smps45_reg: smps45 {
                    /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
                    regulator-name = "smps45";
                    regulator-min-microvolt = < 850000>;
                    regulator-max-microvolt = <1250000>;
                    
                    regulator-always-on;
                    regulator-boot-on;
                };

                smps6_reg: smps6 {
                    /* VDD_CORE */
                    regulator-name = "smps6";
                    regulator-min-microvolt = <850000>;
                    regulator-max-microvolt = <1150000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                /* SMPS7 unused */

                smps8_reg: smps8 {
                    /* VDD_1V8 */
                    regulator-name = "smps8";
                    regulator-min-microvolt = <1800000>;
                    regulator-max-microvolt = <1800000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                /* SMPS9 unused */

                ldo1_reg: ldo1 {
                    /* VDD_SD / VDDSHV8  */
                    regulator-name = "ldo1";
                    regulator-min-microvolt = <1800000>;
                    regulator-max-microvolt = <3300000>;
                    regulator-boot-on;
                    regulator-always-on;
                };

                ldo2_reg: ldo2 {
                    /* VDD_SHV5 */
                    regulator-name = "ldo2";
                    ti,smps-range = <1>;
                    regulator-min-microvolt = <3300000>;
                    regulator-max-microvolt = <3300000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                ldo3_reg: ldo3 {
                    /* VDDA_1V8_PHYA */
                    regulator-name = "ldo3";
                    regulator-min-microvolt = <1800000>;
                    regulator-max-microvolt = <1800000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                ldo4_reg: ldo4 {
                    /* VDDA_1V8_PHYB */
                    regulator-name = "ldo4";
                    regulator-min-microvolt = <1800000>;
                    regulator-max-microvolt = <1800000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                ldo9_reg: ldo9 {
                    /* VDD_RTC */
                    regulator-name = "ldo9";
                    regulator-min-microvolt = <1050000>;
                    regulator-max-microvolt = <1050000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                ldoln_reg: ldoln {
                    /* VDDA_1V8_PLL */
                    regulator-name = "ldoln";
                    regulator-min-microvolt = <1800000>;
                    regulator-max-microvolt = <1800000>;
                    regulator-always-on;
                    regulator-boot-on;
                };

                ldovrtc_reg: ldovrtc {
                    regulator-name = "ldovrtc";
                    regulator-min-microvolt = <1800000>;
                    regulator-max-microvolt = <1800000>;
                    regulator-boot-on;
                };
                
                ldousb_reg: ldousb {
                    /* VDDA_3V_USB: VDDA_USBHS33 */
                    regulator-name = "ldousb";
                    ti,smps-range = <1>;
                    regulator-min-microvolt = <3300000>;
                    regulator-max-microvolt = <3300000>;
                    regulator-boot-on;
                };

                regen1: regen1 {
                    /* VDD_3V3_ON */
                    regulator-name = "regen1";
                    regulator-boot-on;
                    regulator-always-on;
                };
            };
        };

        tps659038_gpio: tps659038_gpio {
            compatible = "ti,palmas-gpio";
            gpio-controller;
            #gpio-cells = <2>;
        };

        extcon_usb2: tps659038_usb {
            compatible = "ti,palmas-usb-vid";
            /* Causes Backtrace */
            interrupts-extended = <&gpio1 4 IRQ_TYPE_EDGE_RISING>;
        };
    };

    /* RTC */
    /* intersil,isl1208 */
    rtc@6f {
       compatible = "isl1208";
       reg = <0x6f>;           
  
       interrupt-parent = <&gpio3>;
       interrupts = <20 IRQ_TYPE_EDGE_BOTH>;            
    };
    
    /* Nine-Axis motion tracking device (accelerometer, gyroscope, compass) */
    accel@68 {
        compatible = "invensense,mpu9250";
        reg = <0x68>;
    };
};

&i2c2 {
    status = "okay";
    clock-frequency = <100000>;

    /* Programmable Battery Management Unit (Fuel Gauge) */
   fuel_gauge@0b {
        compatible = "ti,bq40z60";
        reg = <0x0b>;
    };
};

&i2c3 {
    status = "okay";
    clock-frequency = <400000>;
};

&i2c5 {
    status = "okay";
    clock-frequency = <400000>;
};

&oppdm_mpu {
    vdd-supply = <&smps12_reg>;
};

&oppdm_dspeve {
    vdd-supply = <&smps45_reg>;
};

&oppdm_gpu {
    vdd-supply = <&smps45_reg>;
};

&oppdm_ivahd {
    vdd-supply = <&smps45_reg>;
};

&oppdm_core {
    vdd-supply = <&smps6_reg>;
};

&cpu0 {
    cpu0-voltdm = <&oppdm_mpu>;
    voltage-tolerance = <1>;
};

&uart3 {
    status = "okay";
    interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
                  <&dra7_pmx_core 0x3f8>;
};

&mac {
    status = "okay";
    dual_emac;
};

&cpsw_emac0 {
    phy_id = <&davinci_mdio>, <0>;
    phy-mode = "rmii";

    interrupt-parent = <&gpio2>;
    interrupts = <31 IRQ_TYPE_LEVEL_LOW>;

    dual_emac_res_vlan = <1>;
/*
    fixed-link {
        speed = <10>;
        full-duplex;
    };
*/  
};

&cpsw_emac1 {
    phy_id = <&davinci_mdio>, <1>;
    phy-mode = "rgmii";
    dual_emac_res_vlan = <2>;
};

&mmc1 {
    status = "okay";

    vmmc-supply = <&ldo1_reg>;    
    bus-width = <4>;
    cd-gpios = <&gpio6 27 0>;  /* gpio 219 */
    
    max-frequency = <96000000>;
    /delete-property/ sd-uhs-sdr104;
    /delete-property/ sd-uhs-sdr50;
    /delete-property/ sd-uhs-ddr50;
    /delete-property/ sd-uhs-sdr25;
    /delete-property/ sd-uhs-sdr12;
};

&mmc2 {
    status = "okay";

    pinctrl-names = "default";
    pinctrl-0 = <
                 &mmc1_pins_default
                 &mmc2_pins_default
                 &i2c2_pins_default
                 &i2c5_pins_default
                 &clkout3_pins_default
                 &dcan1_pins_default
                 &emu_pins_default
                 &gpio1_pins_default
                 &gpio2_pins_default
                 &gpio3_pins_default
                 &gpio4_pins_default
                 &gpio5_pins_default
                 &gpio6_pins_default
                 &gpio7_pins_default
                 &gpio8_pins_default
                 &mdio_pins_default
                 &nmin_pins_default
                 &onreset_pins_default
                 &rgmii0_pins_default
                 &rtc_misc_pins_default
                 &rgmii1_pins_default
                 &rmii_pins_default
                 &uart1_pins_default
                 &uart3_pins_default
                 &uart5_pins_default
                 &usb1_pins_default
                 &wakeup_pins_default
                 &vin2a_iodelay_manual1_conf
                 &rgmii0_iodelay_manual1_conf
                 &mmc3_iodelay_manual1_conf
                 &rmii_iodelay_manual1_conf              
                >;
    vmmc-supply = <&vdd_3v3>;
    bus-width = <8>;
    ti,non-removable;

    max-frequency = <48000000>;
    /* silicon 1.1 limitation */
    /* max-frequency = <96000000>; */

    /delete-property/ mmc-hs200-1_8v;

    /delete-property/ sd-uhs-sdr50;
    /delete-property/ sd-uhs-ddr50;
    /delete-property/ sd-uhs-sdr25;
    /delete-property/ sd-uhs-sdr12;    
};

&sata {
    status = "okay";
};

&usb2_phy1 {
    phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
    phy-supply = <&ldousb_reg>;
};

&usb1 {
    /*
     * Options ared:
     * "peripheral", "host", "dual-role"
     */
    dr_mode = "dual-role";
};

&omap_dwc3_1 {
    extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
    extcon = <&extcon_usb2>;
};

&usb2 {
    /*
     * Stand alone usage is peripheral only.
     * However, with some resistor modifications
     * this port can be used via expansion connectors
     * as "host" or "dual-role". If so, provide
     * the necessary dr_mode override in the expansion
     * board's DT.
     */
    dr_mode = "peripheral";
};

&cpu_trips {
    cpu_alert1: cpu_alert1 {
        temperature = <50000>; /* millicelsius */
        hysteresis = <2000>; /* millicelsius */
        type = "active";
    };
};

&mcasp3 {
    #sound-dai-cells = <0>;
    assigned-clocks = <&mcasp3_ahclkx_mux>;
    assigned-clock-parents = <&sys_clkin2>;
    status = "okay";

    op-mode = <0>;  /* MCASP_IIS_MODE */
    tdm-slots = <2>;
    /* 4 serializers */
    serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
        1 2 0 0
    >;
    tx-num-evt = <8>;
    rx-num-evt = <8>;
};

&mailbox3 {
    status = "okay";
    mbox_pru1_0: mbox_pru1_0 {
        status = "okay";
    };
    mbox_pru1_1: mbox_pru1_1 {
        status = "okay";
    };
};

&mailbox4 {
    status = "okay";
    mbox_pru2_0: mbox_pru2_0 {
        status = "okay";
    };
    mbox_pru2_1: mbox_pru2_1 {
        status = "okay";
    };
};

&mailbox5 {
    status = "okay";
    mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
        status = "okay";
    };
    mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
        status = "okay";
    };
};

&mailbox6 {
    status = "okay";
    mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
        status = "okay";
    };
    mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
        status = "okay";
    };
};


&mmu0_dsp1 {
    status = "okay";
};

&mmu1_dsp1 {
    status = "okay";
};

&mmu0_dsp2 {
    status = "okay";
};

&mmu1_dsp2 {
    status = "okay";
};

&mmu_ipu1 {
    status = "okay";
};

&mmu_ipu2 {
    status = "okay";
};

&ipu2 {
    status = "okay";
    memory-region = <&ipu2_cma_pool>;
    mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
    timers = <&timer3>;
    watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
    status = "okay";
    memory-region = <&ipu1_cma_pool>;
    mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
    timers = <&timer11>;
};

&dsp1 {
    status = "okay";
    memory-region = <&dsp1_cma_pool>;
    mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
    timers = <&timer5>;
};

&dsp2 {
    status = "okay";
    memory-region = <&dsp2_cma_pool>;
    mboxes = <&mailbox6 &mbox_dsp2_ipc3x>;
    timers = <&timer6>;
};

&gpmc {
    status = "okay";

    ranges = <2 0 0x02000000 0x01000000>,  /* fpga1 */
             <4 0 0x03000000 0x01000000>;  /* fpga2 */
    
    fpga1 {        
        reg = <2 0 0x01000000>;
        
        #address-cells = <1>;
        #size-cells = <1>;
        
        bank-width = <2>;  /* 1 = 8-bit bus width, 2 = 16-bit bus width */
                
        /**
         * CUSTOM BOARD NOTES:
         * - FPGA clock input is an AND of GPMC_CLK (high) AND the CS (low)
         * - FPGA wants data on the bus for 4 clocks         
         * - Value of 11386 picoseconds for gpmc,sync-clk-ps gives an even divider of 4; in other words the          
         *   GPMC_FCLK will divide evenly to give us GPMC_CLK
         * - For reference, the GPMC_FCLK has a period of 3759 picoseconds
         * - Value of 12 GPMC_FCLKs for gpmc,cs-on-ns was necessary to ensure the data was valid before
         *   clocking the FPGA
         * - The 75ns values were used to ensure we got the 4 clocks that the FPGA wants (noted above)
         * - The 6 GPMC_FLCKs for gpmc,cycle2cycle-delay-ns were necessary to ensure the CS went high
         *   in between consecutive accesses
         */
        gpmc,sync-clk-ps = <11386>; /* Minimum clock period for synchronous mode, in picoseconds */ 
        
        gpmc,cs-on-ns =  <12>;      /* Assertion time */
        gpmc,cs-rd-off-ns = <75> ;   /* Read deassertion time */
        gpmc,cs-wr-off-ns = <75>;   /* Write deassertion time */

        /* WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
        gpmc,we-on-ns = <0>;       /* Assertion time */
        gpmc,we-off-ns = <75>;      /* Deassertion time */
         
        /* OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
        gpmc,oe-on-ns = <0>;       /* Assertion time */
        gpmc,oe-off-ns = <75>;      /* Deassertion time */

        /* Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: */
        gpmc,page-burst-access-ns = <0>;   /* Multiple access word delay */
        gpmc,access-ns = <0>;              /* Start-cycle to first data valid delay */
        gpmc,rd-cycle-ns = <75>;           /* Total read cycle time */
        gpmc,wr-cycle-ns = <75>;            /* Total write cycle time */
        
        /* GPMC_CONFIG6 */
        gpmc,wr-access-ns = <0>;         /* In synchronous write mode, for single or burst accesses, defines 
                                          * the number of GPMC_FCLK cycles from start access time to the 
                                          * GPMC_CLK rising edge used by the memory device for the first data capture. */
        
        gpmc,bus-turnaround-ns = <0>;    /* Turn-around time between successive accesses */
        gpmc,cycle2cycle-delay-ns = <6>; /* Delay between chip-select pulses (in GPMC_FCLKs) - enable boolean(s) below! */
        gpmc,clk-activation-ns = <2>;    /* GPMC clock activation time */
        
        /* gpmc,cs-extra-delay; */             /* CS signal is delayed by half GPMC clock */ 
        gpmc,cycle2cycle-diffcsen;   /* Add "cycle2cycle-delay" between successive accesses to a different CS */       
        gpmc,cycle2cycle-samecsen;   /* Add "cycle2cycle-delay" between successive accesses to the same CS */               
        
        gpmc,device-width = <2>;     /* Total width of device(s) connected to a GPMC
                                      chip-select in bytes. The GPMC supports 8-bit
                                      and 16-bit devices and so this property must be
                                      1 or 2. */
                                      
        gpmc,sync-read;            /* Enables synchronous read. Defaults to asynchronous
                                      is this is not set. */
        gpmc,sync-write;           /* Enables synchronous writes. Defaults to asynchronous
                                      is this is not set. */
    };
    
    fpga2 {        
        reg = <4 0 0x01000000>;
        
        #address-cells = <1>;
        #size-cells = <1>;
        
        bank-width = <2>;  /* 1 = 8-bit bus width, 2 = 16-bit bus width */
                
        /**
         * CUSTOM BOARD NOTES:
         * - FPGA clock input is an AND of GPMC_CLK (high) AND the CS (low)
         * - FPGA wants data on the bus for 4 clocks         
         * - Value of 11386 picoseconds for gpmc,sync-clk-ps gives an even divider of 4; in other words the          
         *   GPMC_FCLK will divide evenly to give us GPMC_CLK
         * - For reference, the GPMC_FCLK has a period of 3759 picoseconds
         * - Value of 12 GPMC_FCLKs for gpmc,cs-on-ns was necessary to ensure the data was valid before
         *   clocking the FPGA
         * - The 75ns values were used to ensure we got the 4 clocks that the FPGA wants (noted above)
         * - The 6 GPMC_FLCKs for gpmc,cycle2cycle-delay-ns were necessary to ensure the CS went high
         *   in between consecutive accesses
         */
        gpmc,sync-clk-ps = <11386>; /* Minimum clock period for synchronous mode, in picoseconds */ 
        
        gpmc,cs-on-ns =  <12>;      /* Assertion time */
        gpmc,cs-rd-off-ns = <75> ;   /* Read deassertion time */
        gpmc,cs-wr-off-ns = <75>;   /* Write deassertion time */

        /* WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
        gpmc,we-on-ns = <0>;       /* Assertion time */
        gpmc,we-off-ns = <75>;      /* Deassertion time */
         
        /* OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
        gpmc,oe-on-ns = <0>;       /* Assertion time */
        gpmc,oe-off-ns = <75>;      /* Deassertion time */

        /* Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: */
        gpmc,page-burst-access-ns = <0>;   /* Multiple access word delay */
        gpmc,access-ns = <0>;              /* Start-cycle to first data valid delay */
        gpmc,rd-cycle-ns = <75>;           /* Total read cycle time */
        gpmc,wr-cycle-ns = <75>;            /* Total write cycle time */
        
        /* GPMC_CONFIG6 */
        gpmc,wr-access-ns = <0>;         /* In synchronous write mode, for single or burst accesses, defines 
                                          * the number of GPMC_FCLK cycles from start access time to the 
                                          * GPMC_CLK rising edge used by the memory device for the first data capture. */
        
        gpmc,bus-turnaround-ns = <0>;    /* Turn-around time between successive accesses */
        gpmc,cycle2cycle-delay-ns = <6>; /* Delay between chip-select pulses (in GPMC_FCLKs) - enable boolean(s) below! */
        gpmc,clk-activation-ns = <2>;    /* GPMC clock activation time */
        
        /* gpmc,cs-extra-delay; */             /* CS signal is delayed by half GPMC clock */ 
        gpmc,cycle2cycle-diffcsen;   /* Add "cycle2cycle-delay" between successive accesses to a different CS */       
        gpmc,cycle2cycle-samecsen;   /* Add "cycle2cycle-delay" between successive accesses to the same CS */               
        
        gpmc,device-width = <2>;     /* Total width of device(s) connected to a GPMC
                                      chip-select in bytes. The GPMC supports 8-bit
                                      and 16-bit devices and so this property must be
                                      1 or 2. */
                                      
        gpmc,sync-read;            /* Enables synchronous read. Defaults to asynchronous
                                      is this is not set. */
        gpmc,sync-write;           /* Enables synchronous writes. Defaults to asynchronous
                                      is this is not set. */
    };
};

/**
  * Further GPIO Configuration:
  * - DSP/FPGA GPIO Hogging
  *   Linux does things like disable GPIO bank clocks if there are no apparent users of the
  *   GPIO. Since ARM and DSP-"owned" GPIOs are separated by banks on this custom board, we need to use the
  *   GPIO "hogging" feature of the device tree: it makes Linux initialize the state and leave
  *   the clocks alone. Other than the GPIO hogging, the ARM side shouldn't touch the GPIOs.
  */
&gpio6 {


    /* GPIO hogs for DSP/FPGA interaction */
    dsp_gpio_fpga1_rf_rx_overload {
        gpio-hog;
        gpios = <4 0>;
        input;
        line-name = "FPGA1_RF_RX_OVERLOAD";
    };
    dsp_gpio_fpga2_rf_rx_overload {
        gpio-hog;
        gpios = <7 0>;
        input;
        line-name = "FPGA2_RF_RX_OVERLOAD";
    };
    dsp_gpio_rf1_fpga_reset {
        gpio-hog;
        gpios = <18 0>;
        output-low;
        line-name = "RF1_FPGA_RESET";
    };
    dsp_gpio_rf2_fpga_reset {
        gpio-hog;
        gpios = <19 0>;
        output-low;
        line-name = "RF2_FPGA_RESET";
    };
};

&gpio8 {

    /* GPIO hogs for DSP/FPGA interaction */
    dsp_gpio_fpga1_status_n {
        gpio-hog;
        gpios = <2 0>;
        input;
        line-name = "FPGA1_STATUS_N";
    };
    dsp_gpio_fpga2_status_n {
        gpio-hog;
        gpios = <14 0>;
        input;
        line-name = "FPGA2_STATUS_N";
    };
    dsp_gpio_fpga1_perstl1_n {
        gpio-hog;
        gpios = <5 0>;
        output-low;
        line-name = "FPGA1_PERSTL1_N";
    };
    dsp_gpio_fpga2_perstl1_n {
        gpio-hog;
        gpios = <17 0>;
        output-low;
        line-name = "FPGA2_PERSTL1_N";
    };
    dsp_gpio_fpga1_rst_n {
        gpio-hog;
        gpios = <11 0>;
        output-low;
        line-name = "FPGA1_RST1_N";
    };
    dsp_gpio_fpga2_rst_n {
        gpio-hog;
        gpios = <23 0>;
        output-low;
        line-name = "FPGA1_RST2_N";
    };
    dsp_gpio_fpga1_dsp_irq {
        gpio-hog;
        gpios = <8 0>;
        input;
        line-name = "FPGA1_DSP_IRQ";
    };
    dsp_gpio_fpga2_dsp_irq {
        gpio-hog;
        gpios = <20 0>;
        input;
        line-name = "FPGA2_DSP_IRQ";
    };
};

0 Yordan Kovachev over 8 years ago in reply to Gerard

TI__Guru**** 161600 points

Hi,

Sorry for the delayed reply, I was OoO.

I've attached our custom board device tree file which was based on the AM5728 EVM file. We're not explicitly using DMA within our custom firmware images running on the DSPs. Do you see anythingusing dma channels within our device tree file?

The dmas used are defined in dra74.dtsi & dra7.dtsi files, so according to which peripherals you use, I can't see any conflicts...

Where would I find what register/address is being accessed? The only visibility I have is in the form of these L3 custom errors that pop up in the kernel log on the ARM side. From what we can tell the DSP side keeps running.

This could be found in the DSP binary, if you use a custom dsp firmware, if you use the unmodified prebuilt DSP binaries, then you should be fine..

I'll try to recreate this on my board and get back to you.

Best Regards,
Yordan

0 Gerard over 8 years ago in reply to Yordan Kovachev

Expert 1290 points

I've gathered a little more information; my normal start-up flow looks like this:

Fresh power up
Load rproc/rpmsg kernel modules, automatically loading DSP1 and DSP2
Stop DSP1 and DSP2 (via unbind node) 20 seconds later (to save power - we may not need DSPs for many minutes/hours later)
A random number of seconds/minutes/hours passes...
Start DSP1 and DSP2 (via bind node)

If I skip step 3 and leave the DSPs up, I no longer get a DSP1 L3 custom error and only get a single DSP2 L3 custom error (as opposed to so many that the system gets stuck and requires power cycle):

[ 46.612683] WARNING: CPU: 0 PID: 0 at linux-4.4.41+gitAUTOINC+f9f6f0db2d-gf9f6f0db2d/drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x258/0x368()
[ 46.630053] 44000000.ocp:L3 Custom Error: MASTER DSP2_DMA TARGET DMM_P2 (Read): Data Access in User mode during Functional access
[ 46.641753] Modules linked in: virtio_rpmsg_bus cmemk(O) omap_remoteproc remoteproc virtio_ring virtio xhci_plat_hcd xhci_hcd usbcore dwc3 usb_f_rndis libcomposite u_ether udc_core uio_pdrv_genirq uio extcon_palmas phy_omap_usb2 dwc3_omap bridge stp llc xt_tcpudp ipv6 iptable_filter ip_tables x_tables hw_info fpga_config bq40z60_battery mpu9250(C) extcon_usb_gpio extcon rtc_isl1208
[ 46.678714] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G WC O 4.4.41-gf9f6f0db2d #1
[ 46.686926] Hardware name: Generic DRA74X (Flattened Device Tree)
[ 46.693045] Backtrace:
[ 46.695520] [<c0013088>] (dump_backtrace) from [<c0013284>] (show_stack+0x18/0x1c)
[ 46.703122] r6:20070193 r5:c0acdba8 r4:00000000 r3:00000000
[ 46.708847] [<c001326c>] (show_stack) from [<c02dee28>] (dump_stack+0x9c/0xb0)
[ 46.716106] [<c02ded8c>] (dump_stack) from [<c003486c>] (warn_slowpath_common+0x8c/0xbc)
[ 46.724229] r6:c030cd48 r5:00000009 r4:c0aafd40 r3:c0aae000
[ 46.729947] [<c00347e0>] (warn_slowpath_common) from [<c00348d4>] (warn_slowpath_fmt+0x38/0x40)
[ 46.738680] r8:c07fd3cc r7:00000002 r6:e0081364 r5:c07fcf6c r4:c07fd088
[ 46.745451] [<c00348a0>] (warn_slowpath_fmt) from [<c030cd48>] (l3_interrupt_handler+0x258/0x368)
[ 46.754360] r3:de1f8b00 r2:c07fd088
[ 46.757964] r4:80080003
[ 46.760521] [<c030caf0>] (l3_interrupt_handler) from [<c0079210>] (handle_irq_event_percpu+0x90/0x148)
[ 46.769865] r10:c0af7554 r9:de1f6540 r8:00000017 r7:00000000 r6:00000000 r5:de1f65a0
[ 46.777768] r4:de206000
[ 46.780324] [<c0079180>] (handle_irq_event_percpu) from [<c0079308>] (handle_irq_event+0x40/0x64)
[ 46.789231] r10:c0aae000 r9:c0653a2c r8:de008000 r7:00000001 r6:c0ab5574 r5:de1f65a0
[ 46.797132] r4:de1f6540
[ 46.799689] [<c00792c8>] (handle_irq_event) from [<c007c5d8>] (handle_fasteoi_irq+0xc0/0x194)
[ 46.808247] r6:c0ab5574 r5:de1f65a0 r4:de1f6540 r3:00000000
[ 46.813977] [<c007c518>] (handle_fasteoi_irq) from [<c007884c>] (generic_handle_irq+0x2c/0x3c)
[ 46.822625] r7:00000001 r6:00000000 r5:00000000 r4:c0aa94ac
[ 46.828341] [<c0078820>] (generic_handle_irq) from [<c0078b24>] (__handle_domain_irq+0x64/0xbc)
[ 46.837081] [<c0078ac0>] (__handle_domain_irq) from [<c0009470>] (gic_handle_irq+0x40/0x7c)
[ 46.845468] r8:fa213000 r7:fa212000 r6:c0aafef0 r5:fa21200c r4:c0ab0978 r3:c0aafef0
[ 46.853295] [<c0009430>] (gic_handle_irq) from [<c064cf40>] (__irq_svc+0x40/0x74)
[ 46.860810] Exception stack(0xc0aafef0 to 0xc0aaff38)
[ 46.865885] fee0: 00000001 00000000 fe600000 00000000
[ 46.874100] ff00: c0ab056c 00000000 00000000 c0aaff60 c0ab05b8 c0653a2c c0aae000 c0aaff4c
[ 46.882312] ff20: c0aaff2c c0aaff40 c00279a0 c0010568 60070013 ffffffff
[ 46.888951] r8:c0ab05b8 r7:c0aaff24 r6:ffffffff r5:60070013 r4:c0010568 r3:c00279a0
[ 46.896779] [<c0010540>] (arch_cpu_idle) from [<c006eea0>] (default_idle_call+0x28/0x34)
[ 46.904909] [<c006ee78>] (default_idle_call) from [<c006f0fc>] (cpu_startup_entry+0x1fc/0x260)
[ 46.913566] [<c006ef00>] (cpu_startup_entry) from [<c0647ad4>] (rest_init+0x90/0x94)
[ 46.921340] r7:00000000
[ 46.923899] [<c0647a44>] (rest_init) from [<c0892d70>] (start_kernel+0x418/0x424)
[ 46.931411] r4:c0afa050 r3:c0aae000
[ 46.935020] [<c0892958>] (start_kernel) from [<80008090>] (0x80008090)

So, apparently the remote processor framework (or something else) doesn't like that I'm powering off the DSPs 20 seconds after enabling them. As stated, the reason for doing this is to save power. I'll have to experiment with longer delays.

I'd still like to understand why DSP2 behaves differently than DSP1 in regards to what L3 custom errors it spits out. For example, is this behavior a clue that the DSPs are configured differently? Do they have a different power-up DMA configuration?

(Also, note that removing rtc references from the device tree - within dra7.dtsi specifically - had no effect.)

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AM5728: L3 custom errors when starting DSPs