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DM6446 / AIC23 intermixed left and right audio output

Hi,

 

We are using DM6446 and TI MP2 Codec to decode audio with two languages that are encoded on two separate audio channels within a single stream and pass the decoded PCM data to the AIC23; we have observed the languages are alternatively intermixed e.g. left speaker will output English, Spanish, English, Spanish… and right speaker will output Spanish, English, Spanish, English…

 

We need to have a clean separate language output on the left and right speakers so what could cause this?

 

Are the settings below correct?

 

DM6446 ASP McBSP register setting:

 

Serial Port Control Register (SPCR) = 0x02F10031

        FREE = 1;

        FRST = 1;

        GRST = 1;

        XINTM = 3;

        XRST = 1;

        RINTM = 3;

        RRST = 1.

Receive Control Register (RCR) = 0x10400040

        RPHASE = 1;

        RFRLEN2 = 0 (1 word);

        RWDLEN2 = 2 (16 bits);

        RFRLEN1 = 0 (1 word);

        RWDLEN1 = 2 (16bits).

Transmit Control Register (XCR) = 0x10440040

        XPHASE = 1;

        XFRLEN2 = 0 (1 word);

        XWDLEN2 = 2 (16 bits);

        XFIG = 1;

        XFRLEN1 = 0 (1 word);

        XWDLEN1 = 2 (16bits).

Sample Rate Generate Register (SRGR) = 0x301FFF01

        CLKSM = 1;

        FSGM = 1;

        FPER = 31;

        FWID = 15.

Pin Control Register (PCR) = 0x03 (Runs as Slave)

        CLKXP = 1;

        CLKRP = 1.

  • Daniel,

    The mcbsp settings appear correct.  I suspect that there is an issue with the EDMA channel being used in which its not properly getting the right/left channel buffers in a correct sorted way.  Can you provide some additional details on how the EDMA is pulling in the data from the buffer memory to give it to the ASP? You have to program the edma sorting (Acnt,Bcnt,Ccnt) to properly grab the audio data from each buffer address correctly.  e.g (L-R, L-R, L-R...) so when it arrives at the ASP it just gets shifted out correctly..

    The data flow should be something as follows..

    Left buffer address

    L0

    L1                                                   ------->   L0-R0, L1-R1, L2-R2.....

    L2

    Right buffer address

    R0

    R1

    R2

    Rather than,                                  ------> L0-R0, R1-L1, L2-R2.....

     

    regards,

    miguel

     

  • Hi Miguel,

    Thank you for pointing us to the DMA direction and we have corrected the problem by replacing the audio SRAM buffers with IRAM. Thank you again for your quick respond!

     

    Regards,

    Daniel   

  • Daniel, Just curious, so was the issue related as well to the DMA sorting from the source buffers or simply a bandwidth issue that caused you to move the SRAM buffers to internal memory. regards, miguel