Part Number: AM3352
Tool/software: Linux
Hello,
I am having a major (hang) problem with the product development on the custom board using AM3352 and DDR3-SDRAM, and still struggling to find a root cause. I would be grateful for some advice.
Issue:
When repeating Deepsleep1 "suspend/resume", suspend fails once in hundreds or thousands of times and eventually the system hangs.
HW/SW configuration:
HW
Custom board based on Beaglbone Black
-AM3352BZCZD80
-DDR3-SDRAM(MT41K256M16TW-107 IT:P)
-No VTT regulator
-No Termination
-PMIC(TPS65910A3A1RSL)
SW
ti-sdk-am335x-evm-05.07.00.00
Location
Path : arch/arm/mach-omap2/sleep33xx.S
The system hangs between the steps “DDR memory Self-refresh entry" and “WFI"
1. Same as v7_flush_icache_all - saving a branch
2. Save EMIF configuration
3. For DDR3, hold DDR_RESET high via control module
4. Self-refresh Entry
5. Give some time for system to enter SR(About 1.0ms)
6. Weak pull down for macro DATA0 <- It hangs on write access to ddr_data0_ioctrl of Control Module
7. Weak pull down for macro DATA1
8. Weak pull down for macro CMD0
9. Weak pull down for macro CMD1
10.Weak pull down for macro CMD2
11.Put IO in mDDR (cmos) mode
12.Disable EMIF
13.Disable VTP
14.Enable SRAM LDO ret mode
15.PLL bypass
16.WFI
Findings:
- A8 is assumed to be suspended, because when the problem occurs, it fails to connect A8 core with JTAG
-JTAG connection for M3 core has no issues even after the event.
-When the problem occurs, the power voltage (VDD_MPU=0.95V, VDDS_DDR=1.5V, VDD_CORE=1.1V) settings are within the standard range
(As it switches from PMIC to PFM mode automatically during the time of the procedure, the voltage consistent fluctuation ±20mV is observed for each power supply .)
-LOW level on DDR_CKE (Normal), when the problem occurs(around 0V).
-Maintain High on DDR_RESETn (Normal) when the problem occurs.
I cannot figure out whether it is caused by HW or SW.
Would you please provide advice for determining the possible root cause or similar problems you have encountered or anything.
