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TMS320C6678: Ether does not link up after TFTP boot with customer's board

Hitoshi Sugawara
Mastermind 19960 points
Part Number: TMS320C6678

Hi Folks,

Our customer built their own prototype board and has been facing a problem which Ethernet does not link up after TFTP boot.
It seems that their TFTP boot works correctly with TI's EVM.
We would very appreciate if TI could suggest check points to resolve this.

The discrepancy between their board and EVM is as follows:

EVM:  (TFTP boot works correctly )
     DIP SW setting : bm_gpio_i
     DSP GPIO input : dsp_gpio_o
     Verilog code : (DIP SW setting --> DSP GPIO input )
 　assign  force_bootmode [13:1] = (bm_gpio_i[6:5]==2'b00 && bm_gpio_i[3:1]==3'b000)? bm_gpio_i[13:1] : 13'h405; //20110219
 　assign  dsp_gpio_o = {bm_gpio_i[15:14], force_bootmode[13:1], bm_gpio_i[0]};  //20110219

     Note : (bm_gpio_i[6:5]==2'b00 && bm_gpio_i[3:1]==3'b000)　
     If No Boo is 
                 true, bm_gpio_i[13:1] is ignored.
                 false, 13'h405　I2C boot. 
 Procedure:
  (1) I2C boot.  DEVSTAT register = DSP GPIO input is not equal to DSP SW setting.
  (2) Initialization
  (3) DEVSTAT register = DIP SW setting.
  (4) main function is called.
  (5) TFTP boot following DEVSTART setting.  Ethernet works correctly.


Their own board:
   DSP GIIO input = DIP SW setting.

 Procedure:
  (1) I2C boot. DEVSTART register = DSP GPIO input = DIP SW setting.  Will check the value of DEVSTAT tomorrow.
  (2) Initialization
  (3) DEVSTART register = DIP SW setting. ( This process is skipped by modifying IBL. )
  (4) main function is called.
  (5) TFTP boot following DEVSTART setting.   Ethernet does not link up. 

Thank you very much in advace for your kind support.

Best regards,
Hitoshi Sugawara

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've forwarded this to the design team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 19960 points

    Hi Yordan,

    Here is our update as follows:

    With TI' EVM:
    - Confirmed that after the application image was downloaded through IBL, it worked OK.
    [Result] I2C boot finished. TFTP boot worked correctly. SMGII Link was up and packet transaction worked correctly.

    - The application program was downloaded from JTAG and its operation was checked.
    Emulator was connected (CCS Connect), GEL initialization operated.
    The application program was downloaded through JTAG to DSP.

    a. No Boot was selected:
    [Result] Link was up and packet transaction correctly worked.
    b. Ether boot by RBL.
    [Result] Link was up and packet transaction correctly worked.

    Customer's board:
    - Confirmed that after the application image was downloaded through IBL, it did not work.
    [Result] I2C boot finished. they were not sure whether TFTP boot worked correctly or not. SMGII link was not up.

    - The application program was downloaded from JTAG and its operation was checked.
    Emulator was connected (CCS Connect), GEL initialization operated.
    The application program was downloaded through JTAG to DSP.

    a. No Boot was selected:
    [Result] Link was not up. No packet transaction confimed.

    b. Ether boot by RBL. It seemed the program has been working and BootP packet sent out periodically.
    　　 [Result] Link was up, however, its packets transaction was not good.


    Other checking points are:
    1. Their board is designed based on TI’s EVM. But it does not have FPGA XC35200AN made by Xilinx.
    2. MAC1 is utilized as same as EVM.
    TFTP boot still does not work on their board.
    The HW difference is that DSP is not directly connected to PHY. FPGA is located in between.
    DSP⇔FPGA⇔PHY. FPGA is inserted in between.
    3. DEVSTAT value is 0000 1000 0100 1010.
    4. Clock: 1.25GHz and 1GHz were tested but their system does not link up. Target Clock speed is 1.25GHz.
    5. The STATUS register shows 0x30 or 0x38. The reserved bits are set. Link up is 0.
    6. SW modification: Their board does not have FPGA, therefore, its control function from IBL was removed.
    IblEnterRom( ) was removed.

    Thank you very much for your time to check.
    Best regards,

    Hitoshi Sugawara

  • 0 in reply to Hitoshi Sugawara
    TI__Mastermind 19960 points
    Hi Yordan,

    The customer updated.
    After they modified IBL as blow like RBL does, the link was up.

    ・SGMII_SERDES_CFGPLL　0x00000041(MPY=8x)　⇒　0x00000051(MPY=10x)
    ・MAINPLLCTL0　　　　1000MHz ⇒ 500MHz
    ・PASSPLLCTL0　　　　1050MHz ⇒ 420MHz

    These three changes are necessary for link up.
    Could you please let us know what SGMII_SERDES_CFGPLL meaning.

    Thank you and best regards,
    Hitoshi Sugawara
  • 0 in reply to Hitoshi Sugawara
    TI__Mastermind 19960 points
    Hi Team,
    According to the customer, it links up expectedly with their own board after the modification of IBL was done as follows:
    ・SGMII_SERDES_CFGPLL　0x00000041(MPY=8x)　⇒　0x00000051(MPY=10x)
    ・MAINPLLCTL0　　　　1000MHz ⇒ 500MHz
    ・PASSPLLCTL0　　　　1050MHz ⇒ 420MHz

    Could you please let me know why the setting for SGMII_SERDES_CFGPLL works?

    www.ti.com/lit/SPRUGV9 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem
    - Page 196
    refclk = LINERATE * RATESCALE/MPY
    ※ refclk : SGMII CLK
    LINERATE : CORE CLK
    RATESCALE : Table 3-172
    MPY : Table 3-173 SGMII SerDes PLL Multiply Modes

    SGMII_SERDES_CFGPLL.MPY
    Table 3-172 Ratescale Values
    Full : Ratescale = 0.5
    Half : Ratescale = 1
    Quarter : Ratescale = 2
    Thirty-second : Ratescale = 16

    With customer’s board:
    RATESCALE = (refclk * MPY) / LINERATE
    = (250 * 10) / 1250
    = 2
    ※ Quarter in Table 3-172
    With C6678EVM
    RATESCALE = (refclk * MPY) / LINERATE
    = (312.5 * 8) / 1000
    = 2.5
    ※ The value of 2.5 is not in Table 3-172

    Additional questions:
    1) Is refclk output or input clock?
    2) It seems DSP has to transmit the packet first to start communication. Is this correct?
    3) If the MAC address is not registered in L2 SW ARP table at SGMII IF module in DSP, doesn’t it transmit any packets?
    Am I correct?

    Thank you for your check.
    Best regards,
    Hitoshi Sugawara
  • 0 in reply to Hitoshi Sugawara
    TI__Guru* 95265 points
    Hi,

    1) For TI 6678 EVM, the referenc clock to SGMII is 312.5MHz, with MPY = 8, ratescale = 2 (from SGMII_SERDES_CFGRX/TX bit 5:4), LINERATE = 1250MHz, this is correct. Note for SGMII 1Gbps, the line rate is 1.25GHz, not 1.00 GHz.

    For customer board, if reference clock is 250MHz, then MPY = 10, ratescale = 2, the LINERATE = 250 * 10 /2 = 1250 as well. This is correct configuration.

    2) MAINPLLCTL0, this is for main PLL, the C6678 can run at 1000MHz, I don't think you need to change it to 500MHz to make SGMII working.

    3)PASSPLLCTL0, PA can run at 1050MHz, no need to change it to 420MHz for SGMII working.

    4)refclk is output from crystal, serving as input to SGMII.

    5)In TFTP boot mode, the DSP generate bootp packets at regular interval when power up (to TFTP server), to start TFTP transfer

    6) It always transmit packets when powered up.

    Regards, Eric
  • 0 in reply to lding
    TI__Mastermind 19960 points
    Hi Eric,
    All answers were dispatched to the customer and will let you know their answer soon.
    Thank you so much for your kind support.
    Best regards,
    Hitoshi Sugawara
  • 0 in reply to Hitoshi Sugawara
    TI__Mastermind 46460 points

    Hitoshi-san,

    Was this issue resolved?  It appears that Eric provided the required validation.  Since the customer was able to make it function by loading the program over CCS, it appears that the Intermediate Boot Loader created for the SEEPROM has an issue.  TFTP boot is not supported by the ROM Bootloader, this is enabled through the IBL in the I2C SEEPROM.

    Tom