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External memory best use on OMAPL138

Jonathan Journo
Intellectual 475 points
Other Parts Discussed in Thread: OMAPL138

Hello,

We are developping an application on the OMAPL138 that make the use of the ARM and DSP core separately because they are doing different tasks. We planed to use Linux as GPP OS and DSP/BIOS for DSP. Codec Engine was not a good solution for us so instead we decided to use DSPLINK directly to inter-processor communication.

We planed to use a DDR2 RAM shared between the ARM and the DSP. ARM and DSP will make use of the DDR2 at different sections. But I am afraid the DSP will be slowed because of this memory sharing although the presence of cache memory in the DSP.

1/ Does the ARM and DSP could access "simultaneously" the DDR2 memory (maybe with different EDMA channels) ?

2/ Is it possible to use a configuration like ARM connected to EMIFA (SDRAM) running Linux and DSP connected to the second EMIFB (DDR2 controller) or vice versa ?

3/ If the thing is possible, may it will be more efficient in term of code execution speed / DATA Read/Write ?

4/ Form the DSP side, how much the DSP will be slowed if I am running DSP code from external DDR if L1PRAM cache is enable?

 

Thanks for your advices,

 

  • 0
    TI__Guru 62975 points

    Jonathan Journo said:

    1/ Does the ARM and DSP could access "simultaneously" the DDR2 memory (maybe with different EDMA channels) ?

    Yes, the ARM and DSP can share access to DDR2.  The system interconnect will take care of arbitration for you.  Here is a good article on the subject:

    http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SOC_Architecture_and_Throughput_Overview

    Jonathan Journo said:

    2/ Is it possible to use a configuration like ARM connected to EMIFA (SDRAM) running Linux and DSP connected to the second EMIFB (DDR2 controller) or vice versa ?

    3/ If the thing is possible, may it will be more efficient in term of code execution speed / DATA Read/Write ?

    Yes, this is possible.  It's hard to comment on the efficiency because it varies by application.  Also, the EMIFB DDR datapath may be able to handle more bandwidth (compared to EMIFA) because it is intended to be the primary external memory interface.  If you read through the SOC Architecture article, you will see that the CPUs would go through a 64-bit bus to DDR vs a 32-bit bus to EMIFA.

    Jonathan Journo said:

    4/ Form the DSP side, how much the DSP will be slowed if I am running DSP code from external DDR if L1PRAM cache is enable?

    Again, it is hard to judge the performance hit, but the L1/L2 cache is able to handle external memory activity fairly well.