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TMS320C6678: Unused HyperLink SerDes interface Pin Requirement

Daisuke Maeda
Guru 20425 points

Part Number: TMS320C6678

Can all HyperLink SerDes interface pins (MCMRXNx, MCMRXPx, MCMTXNx, MCMTXPx) be left floating when the entire HyperLink peripheral is not used?
"6.2.5 Unused HyperLink Pin Requirement" on "Hardware Design Guide for KeyStone Devices (Rev. C)" (SPRABI2C) seems to not mention the HyperLink SerDes interface pins.
"All HyperLink clock and data pins (MCMRXFLCLK, MCMRXFLDAT,
 MCMTXFLCLK, MCMTXFLDAT, MCMRXPMCLK, MCMRXPMDAT,
 MCMTXPMCLK, MCMTXPMDAT) can be left floating when the entire HyperLink
 peripheral is not used. Each unused HyperLink clock and data pin will be pulled low
 when not in use through internal pull-down resistors.
"
I think all the HyperLink SerDes interface pins can be left floating because those differential inputs are each internally terminated to a common point via a 50ohm resistor.
"8.2.2 Receiver Termination" on "SerDes Implementation Guide for KeyStone I Devices Application Report" (SPRABC1) describes:
"The rxpi and rxni differential inputs are each internally terminated to a common point
 via a 50-??resistor, i.e., a 100-??differential termination. This TERM value should be
 set to 001: Common point set to 0.7 VDDT for all use cases. Common point set to
 0.7 VDDT is the recommended configuration for all AC coupled systems.
"
Best regards,
Daisuke
  • 0
    Guru 20425 points
    Hi,
    Can all HyperLink SerDes interface pins (MCMRXNx, MCMRXPx, MCMTXNx, MCMTXPx) be left floating when the entire HyperLink peripheral is not used?
    "6.2.5 Unused HyperLink Pin Requirement" on "Hardware Design Guide for KeyStone Devices (Rev. C)" (SPRABI2C) describes:
    "In the event a partial number of lanes are used (two lanes instead of four), all clock and
     data pins must be connected. Unused lanes (both transmit and receive) can be left
     floating. 
    "
    It does not describe the requirement of the time the entire HyperLink peripheral is not used.
    Please give me an answer as soon as possible. Your prompt reply would be appreciated.
    Best regards,
    Daisuke
  • 0 in reply to Daisuke Maeda
    TI__Guru**** 161600 points

    Hi Daisuke,

    The hardware design guide clearly states:

     "All HyperLink clock and data pins (MCMRXFLCLK, MCMRXFLDAT, MCMTXFLCLK, MCMTXFLDAT, MCMRXPMCLK, MCMRXPMDAT,

    MCMTXPMCLK, MCMTXPMDAT) can be left floating when the entire HyperLink peripheral is not used. Each unused HyperLink clock and data pin will be pulled low when not in use through internal pull-down resistors. "

    "If the HyperLink interface is not being used, the peripheral should be disabled in the MMR."

    "If the HyperLink interface is not required, the HyperLink regulator power pin (VDDR1_MCM) must still be connected to the correct supply rail with the appropriate

    decoupling capacitance applied. The EMI/Noise filter is not required when this interface is not used." 

    "If unused, the primary HyperLink clock input must be configured as indicated in Section 3.3, Figure 13. Pull-up must be to the CVDD core supply." 

    So to answer your question, if you DO NOT use the entire Hyperlink, then you should leave all clock and data pins unconnected with the internal pull-down resistors enabled. The power should still be connected. The clock must be configured, as described in the Hardware Design Guide. 


    Best Regards, 
    Yordan

  • 0 in reply to Yordan Kovachev
    Guru 20425 points
    Hi Yordan-san,
    Thank you for your reply.
    I want to know SerDes interface pins not clock and data pins of sideband signals.
    Each of clock and data pins (MCMRXFLCLK, MCMRXFLDAT, MCMTXFLCLK, MCMTXFLDAT, MCMRXPMCLK, MCMRXPMDAT, MCMTXPMCLK, MCMTXPMDAT) of sideband signals is LVCMOS buffer, but each of SerDes interface pins (MCMRXNx, MCMRXPx, MCMTXNx, MCMTXPx) is CML buffer.
    Can all HyperLink SerDes interface pins (MCMRXNx, MCMRXPx, MCMTXNx, MCMTXPx) be left floating when the entire HyperLink peripheral is not used?
    Best regards,
    Daisuke
  • 0 in reply to Daisuke Maeda
    TI__Guru**** 161600 points
    Hi,

    Let me have a look at this and will get back.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 20425 points
    Hi Yordan-san,
    Thank you for your cooperation.
    Please give me an answer as soon as possible. Your prompt reply would be appreciated.
    Best regards,
    Daisuke
  • 0 in reply to Yordan Kovachev
    Guru 20425 points
    Hi Yordan-san,
    For all other SerDes interface (SGMII, SRIO, PCIe), "Hardware Design Guide for KeyStone Devices (Rev. C)" (SPRABI2C) describes that those pins must be left floating.
    I think HyperLink SerDes interface pins (MCMRXNx, MCMRXPx, MCMTXNx, MCMTXPx) must be left floating similarly.
    Best regards,
    Daisuke
  • 0 in reply to Daisuke Maeda
    TI__Guru**** 161600 points
    Hi Daisuke,

    Sorry for the late reply.

    For all other SerDes interface (SGMII, SRIO, PCIe), "Hardware Design Guide for KeyStone Devices (Rev. C)" (SPRABI2C) describes that those pins must be left floating.

    Yes, this is correct.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 20425 points
    Hi Yordan-san,
    Thank you for your reply.
    Best regards,
    Daisuke