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Strange behavior during L1D writeback invalidate

I am trying to perform a L1 cache writeback-invalidate in an assembly application on a C6713, and I am encountering very strange errors.

The code I am using is: 


        mvkl L1DWIBAR, a8 ; address of L1D Writeback Invalidate 
        mvkh L1DWIBAR, a8 ; base address register

        mvkl L1DWIWC,  a9 ; address of L1D Writeback Invalidate
        mvkh L1DWIWC,  a9 ; word count register

        stw a12, *a8  ; write start address to base address register
        stw a1,  *a9  ; write word count to word count register
        nop 4        ; wait until takes effect

l1d_spin_top:
        ldw *a9, a2  ; Read remaining word count
        nop 4
   [a2] b l1d_spin_top
        nop 5


When I run my program, it gets stuck in the spin loop. When I stop it using the debugger, the L1DWIWC register contains 0, but a2 will have some data in it. When I single-step through the code, a2 correctly gets the value of the L1DWIWC register, and the program continues.

This leaves me with 2 questions:

  1. Can anyone explain this behavior?
  2. Does anyone have example assembly code to perform a L1 cache writeback-invalidate?

 

  • My suggestion is to write this in C using CSL calls to do the same thing (write-back-invalidate followed by cache-wait call). Then use the CCS debugger to look at the assembly code generated to do the operations.

    Once you have it working in C with CSL, you will have one working example of an assembly implementation by copying exactly the assembly generated for these calls. Then you can optimize it as needed by removing instructions you do not think are needed.

    This will give you #2, and you may find the answer to #1 by examining that code.

     

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