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McBSP-1

Hi,

I've been trying to program McBSP-1 to output serialized data on OMAP3EVM for days. However, so far, there is no luck. No data is coming out from DX pin.

The test program has been simplified to write to McBSP control registers directly. Data are written into MCBSPLP_DXR_REG (0x48074008). I can see the number of free words reduced by checking MCBSPLP_XBUFFSTAT_REG (0x480740b4), which implies data are putting into the queue. But no data is output from the DX pin and the number of free words never increases. Seems like the Transmit Shift Register (XSR) does not shift data out.

I run out of ideas. Hope someone can provide some suggestion. Thank you very much.

 

The following is the registers values

CM_CLKSEL1_PLL :  0x094C0C00
FLCKEN1_CORE:     0x00006200
ILCLKEN1_CORE:    0x01006252

**** McBSP0 regs ****
DRR2:  0x0020
DRR1:  0x0000
DXR2:  0x0000
DXR1:  0x0000
SPCR2: 0x00c5
SPCR1: 0x0000
RCR2:  0x0001
RCR1:  0x2f40
XCR2:  0x0001
XCR1:  0x2f40
SRGR2: 0x2000
SRGR1: 0x00f9
PCR0:  0x0a01
***********************

 

 

  • Hsueh-szu

    Looking at your register settings you have setup the McBSP1 to be a transmit master with a frame of 48 16bit words and a sync pulse 16bits wide. The problem is that you have only set your frame period (SRGR2:FPER) to 1bit time. This controls the number of clocks between the start of sync pulses and needs to be at least equal to the size of the frame. In your case this is 48 words of 16bits which equals 768. Therefore the correct value of SRGR2 would be 0x22ff.

     

    Also you need to make sure that the input is enabled in the relevant CONTROL_PADCONF_* register for both FSX and CLKX pins. This allows the CLKX and FSX to be routed from the output pin back to the transmitter.

     

    You don’t list the value of CONTROL_DEVCONF0 but if it is unchanged then the default mode for McBSP1 is 6 pin.

      Paul

  • You are right. SRGR2:FPER is the problem. I misunderstood the meaning of this register. Thank you very much for your information.