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TDA3: IPU Interprocessor Communication (IPC)

Yuvraj Gaikwad
Prodigy 155 points

Part Number: TDA3

Hello,

As per above description is seems that a interrupt ca be is used for IPC using CORTEXM4_CTRL_REG.

 What will be the interrupt signal that will be generated ?

Whether this interrupt needs to be enabled/disabled ? Then from where ?

Crossbar configuration required ? which interrupt signal to use with crossbar ?

Is this an interrupt or a dedicated exception ?

The description says that the priority for the interrupt is configurable but I could not find any interrupt signal associated with this interrupt ?

Regards,

Yuvraj

  • 0
    TI__Guru 55685 points
    Hi Yuvraj,

    The interrupt you are looking for is HWSEM_M4_IRQ which is present on IRQ line number IPU_IRQ_19.
    This interrupt will be generated when one IPU core sets the interrupt bit for other core in CORTEXM4_CTRL_REG as given in the description you shared.
    As this is an internal interrupt crossbar configuration is not needed.
    You can use the interrupt controller APIs depending on what software you are using to set up the priority. E.g. Intc_IntPrioritySet API should be used if you are using starterware.

    Regards,
    Rishabh