RTOS/TDA2EG: Query regarding alignment and DMA size

Mayank Agarwal

Expert 2600 points

Part Number: TDA2EG

Tool/software: TI-RTOS

Hi.

I was going through document:

http://www.ti.com/lit/an/sprac21/sprac21.pdf

In section 17.4.1.3 it is written:

Masters where alignment CANNOT be made possible by system design software control: • GPU/BB2D • MMC • GMAC • USB For many of the above interface, it might not be possible to program the descriptor to always produce aligned writes. This is because the DMA size is determined by the incoming packet length or pixel location in frame that is not in user control

Now if we are getting

ndk2NspStats.txFreeCPDMAPacketDequeue++ increase because of packet drop when i am running svs application on tda2xx,it can be because of above issue described in the document.

Please confirm if dma write won't work we will get the increase in txFreeCPDMAPacketDequeue.

Regards

Mayank

over 8 years ago

0 Yordan Kamenov over 8 years ago

TI__Mastermind 42515 points

Hi Mayank,

I have forwarded your question to DMA expert.

Regards,
Yordan

0 Piyali Goswami over 8 years ago in reply to Yordan Kamenov

TI__Mastermind 30245 points

Hi Mayank,

The alignment requirement is coming from the fact that ECC will be incorrectly calculated if data written to DDR is less than the ECC quanta (32 bits for normal DDR mode and 16 bits for narrow mode operation). If you do not have ECC enabled in your system and there are no ECC errors, you would not be encountering the limitation mentioned in the document link.

Thanks and Regards,

Piyali

0 Prasad Jondhale over 8 years ago in reply to Piyali Goswami

TI__Mastermind 27743 points

Hello Mayank,

As discussed issue was due to system tuning and not related to alignment. So closing this thread.

Processors

Processors forum

RTOS/TDA2EG: Query regarding alignment and DMA size