• State Resolved
  • Locked Locked
  • Replies 11 replies
  • Subscribers 102 subscribers
  • Views 1466 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

YCC8 Setting for PAL 576i

Kaustubh Patankar
Prodigy 85 points

Hi

I wanted to set the device to output 576i / PAL/YCC8. Can any one help in providing the details? In the current setup the verification of output data is possible using Logic Analyzer. We have verified that the fixed pattern created is coming properly for YCC16.

We referred to the WiKi for YCC8 (this is given for settings of NTSC). the output data pattern is dropping few of the fixed pattern values.

regard

Kaustubh

  • 0
    TI__Genius 14405 points

    Hi,

    Could you please describe exactly how many lines you are dropping, and maybe explain it using a picture.

    I'd start w/ the VIDWIN0YL value and see if you set it to 576/2.

    Just wondering, is this a testcase you created by yourself? Do you have a register dump?

  • 0 in reply to Paul.Yin
    Prodigy 85 points

     

     

    Hi Paul 

    I have set the following registers. I have used the loop back sample application. 

    Requirement - 576i/50, BT656, YCC8 pattern.

    Current register settings.

     

    (VENC_VMOD, 0x00001243);
    (VENC_VIDCTL, 0x6000);
    (VENC_SYNCCTL, 0xF);
    (VENC_LCDOUT, 0x1);
    (VENC_VINT, 0x259);
    (VENC_HINT, 0x06BD);  
    (VENC_HSTART, 0x11E);
    (VENC_VSTART, 0x18);
    (VENC_VSPLS, 0x18);
    (VENC_HSPLS, 0x11E);
    (VENC_VVALID, 0x120);

    (VENC_HVALID, 0x5A0);

    Where HINT+1 = 1726, V-start - 24, HVALID - 1440, HSTART - 286, VINT+1 - 601, VVALID - 288

    Regard

    KP

     

  • 0 in reply to Kaustubh Patankar
    TI__Genius 14405 points

    I don't think you need to program all the above regsiters, considering you are in the standard mode. What i'd suggest is to get analog PAL working. Then have a look at the following post http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/p/55963/200363.aspx#200363.

  • 0 in reply to Paul.Yin
    Prodigy 85 points

    Hi Paul,

    We modified the register as per Wiki for NTSC mode.

    http://processors.wiki.ti.com/index.php/How_to_program_VPBE_YCC8_digital_out

    We have also tried to modify the setting as suggested by you in the link provide. But the issue is not getting addressed. Following is the sequence of events for your help

    - the fixed pattern and a standard video file was able to see on YCC8 using EVM board. the output was seen after analog conversion

    - In my current system we are sending data to FPGA and hence we are observing output on Logic Analyzer as Analog out is not available.

    - We could observer 15.5 KHz for HD and 50 for VD - PAL settings -  is this correct.

    - the issue is data pattern  observed on the analyzer. Please see below details 


    2) Fixed pattern  : Different data for UYVY (alternate values of U and V are different)

    Data send by DSP : 00 11 22 33 44 55 66 77 00 11 22 33 44 55 66 77  ............................................... 00 11 22 33 44 55 66 77
    Expected o/p        : 00 11 22 33 44 55 66 77 00 11 22 33 44 55 66 77  ............................................... 00 11 22 33 44 55 66 77


    We have observed that when UV data is getting changed, U2 appears in V1 place and we are not getting V component at all. Also we can see some data fluctuations (e.g. between data 11 and 44 or 33 and 44 etc) in same clock. Is this expected output? (vclk and c3(0) are same waveforms)

  • 0 in reply to Kaustubh Patankar
    TI__Mastermind 19985 points

    Kaustubh,

    As we discussed offline, the following suggestions would solve the issue. I am listing them here so that this post can have the relevant answers availablae. Please confirm and close this thread once you verify the solutions.

     

    1. Modify YCCCTL.CHM bit to 1

    2. Modify YCCCTL.REC656 bit to 1

    Please refer to page 46 of the VPBE PRG which tells that YUV422 data is converted to YUV44 data and is then sent out on digital interface as YUV422 based on the setting of CHM.

    If CHM=0, Cr data sent out on the bus is calculated as follows

    Cr1 = (Cr0+Cr2)/2

    Cr3 = (Cr2+Cr4)/2.........

    The data going out on the bus goes as follows:

    Cb0 Y0 Cr1 Y1 Cb2 Y2 Cr3 Y3.....

    If CHM=1, data goes out as follows:

    Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y2........., which is what you were looking for.

    Regards,

    Anshuman

    PS: Please mark this post as verified, if you think it has answered your question. Thanks.

     

  • 0 in reply to Kaustubh Patankar
    Intellectual 405 points

    I am facing exactly same problem as this.

    Is this issue resolved? If yes, can anybody help me with the solution?

    Regards,

    Mitul Chokshi

  • 0 in reply to Mitul Chokshi
    TI__Genius 9510 points

    It seems that the responses on this thread addressed and fixes the original problem reported.  Have you implemented the suggestions described in the follow up responses of this thread?

  • 0 in reply to Marcus Cooksey
    Intellectual 405 points

    Yes, I have implemented the suggestions described in this thread. But my problem is not resolved.

    Please note that I'm using non-standard mode & not using BT.656 as well.

  • 0 in reply to Mitul Chokshi
    TI__Mastermind 19985 points

    Hi Mitul,

    Can you describe your problem as the earlier problem was solved with the explaination that i had provided?

    Regards,

    Anshuman

  • 0 in reply to Anshuman Saxena
    Intellectual 330 points

    Dear Anshuman,

    you have already helped me once, and I hope you will do this time too...

    I am trying to output digital video from the dm365. I am able to output nonstandard ycc16 640x480 vga and 1280x720p @ 60 Hz, and it works fine...

    Now, I am trying to output digital NTSC (I guess PAL is very similar).

    I have an FPGA between the dm365 and the video encoder, so I do not really care about the output format.

    Can you please give a register set that will do this? The best I have achieved was to output ycc16 at ntsc rate, but the cr and cb,  at 27 mhz vclk are coming out too fast. (meaning they are changing at 27MHz too).....

    I am using Ridgerun kernel, 2.6.32

    Thanks is advance

    Albert

  • 0 in reply to albertburbea
    TI__Mastermind 19985 points

    Hi,

    I will try to provide the best help i can. I am actually out of office, so my responses will be delayed.

    Meanwhile, i want to understand, if you just want BT656 or a parallel output with discrete syncs? Also, is 8-bit output ok or you need 16-bit output?

    You might want to look at VMOD register where in you can select "standard NTSC/PAL mode" using VMD bit (bit 4), TVTYP (bit 6-7) for selecting NTSC/PAL, HDMD (bit 8) for selecting HDTV standard against SDTV standard and VDMD (bit 13-12) for selecting 16 bit or 8 bit mode.

    Let me know if it helps.

    Regards,

    Anshuman

    PS: Please mark this post as verified, if you think it answers your question. Thanks.