CCS/TMS320C6678: about QMSS High Priority Accumulation Queue interrupt

canfoderiskii

Part Number: TMS320C6678
Other Parts Discussed in Thread: SYSBIOS

Tool/software: Code Composer Studio

I manually pushed some descriptors into the High Priority Accumulation Queue (queue 704) whose is mapped to DSP event 48. But I found the bit 16 (corresponds to Event 48) of CorePac Event Flag Register 1 (EVTFLAG1) was not set to 1.

Why? Am I missing something? How to let the receive queue trigger some interrupt and notify the CPU to pop descriptors?

over 9 years ago

0 Yordan Kovachev over 9 years ago

TI__Guru**** 161600 points

Hi,

I've notified the team. Their feedback will be posted here.
Can you share which SDK is this? Or is this a custom sw?

Best Regards,
Yordan

0 canfoderiskii over 9 years ago in reply to Yordan Kovachev

Expert 2255 points

processor-sdk 3.3

0 lding over 9 years ago in reply to canfoderiskii

TI__Guru* 95265 points

Hi,

Please check processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices. This is primary interrupt to CPU from TMS320C6678 datasheet Figure 7-32 TMS320C6678 System Event Inputs — C66x CorePac Primary Interrupts (Sheet 2 of 4). QM Interrupt for Queue 704 with event ID48 goes to CPU 0.

Regards, Eric

0 canfoderiskii over 9 years ago in reply to lding

Expert 2255 points

Hi, lding.

I know that's a primary interrupt to CPU0, that is why I directly checked the EVTFLAG1 register in Core0 via JTAG Debugging mode.
But I didn't create any Hwi for that event in my SYSBIOS application. I think triggering the event flag won't depend on the Hwi creation or Interrupt Mux Register (INTMUXn) settings, am I correct?

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CCS/TMS320C6678: about QMSS High Priority Accumulation Queue interrupt