Part Number: PROCESSOR-SDK-AM57X
Tool/software: TI-RTOS
Hi all,
In our application, we want to use a shared memory between the 3 followings cores : A15 (Linux), IPU (SYS/BIOS) and DSP (SYS/BIOS). I created a CMEM shared memory according to the "AM57x Processor SDK Linux®: Customizing Multicore" (sprac60). Linux allocs this CMEM memory and sends the physical address to the others cores (IPU and DSP), through a messageQ. Each core can use this shared memory. That works well.
Now, we want to use the GateMP mechanism to protect read/write to this shared memory. I found the "gatempapp" example in the IPC/packages directory. I implemented it. I created a shared memory (SR_0), that is owned by the DSP. The GateMP mechanism works between Linux (create/open) and the DSP (create/open), but not in the IPU core.
DSP :
*.cfg :
var BIOS = xdc.useModule('ti.sysbios.BIOS');
BIOS.addUserStartupFunction('&IpcMgr_callIpcStart');
var GateMP = xdc.useModule('ti.sdo.ipc.GateMP');
GateMP.hostSupport = true;
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
var SR0Mem = Program.cpu.memoryMap["SR_0"];
SharedRegion.setEntryMeta(0,
new SharedRegion.Entry({
name: "SR0",
base: SR0Mem.base,
len: SR0Mem.len,
createHeap: true,
ownerProcId: MultiProc.getIdMeta("DSP1"),
cacheEnable: true,
isValid: true
})
);
var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
Resource.customTable = true;
*.c :
GateMP_Params_init(&gateParams); gateParams.name = App_GATE_DSP_NAME; gateParams.localProtect = GateMP_LocalProtect_PROCESS; gateParams.remoteProtect = GateMP_RemoteProtect_SYSTEM; gateParams.regionId = 0; Module.slaveGateMPHandle = GateMP_create(&gateParams);
IPU :
*.cfg :
var BIOS = xdc.useModule('ti.sysbios.BIOS');
BIOS.addUserStartupFunction('&IpcMgr_callIpcStart');
var GateMP = xdc.useModule('ti.sdo.ipc.GateMP');
GateMP.hostSupport = true;
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
var SR0Mem = Program.cpu.memoryMap["SR_0"];
SharedRegion.setEntryMeta(0,
new SharedRegion.Entry({
name: "SR0",
base: SR0Mem.base,
len: SR0Mem.len,
createHeap: true,
ownerProcId: MultiProc.getIdMeta("DSP1"),
cacheEnable: true,
isValid: true
})
);
var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
Resource.customTable = true;
*.c
GateMP_Params_init(&gateParams); gateParams.name = App_GATE_IPU_NAME; gateParams.localProtect = GateMP_LocalProtect_PROCESS; gateParams.remoteProtect = GateMP_RemoteProtect_SYSTEM; gateParams.regionId = 0; Module.slaveGateMPHandle = GateMP_create(&gateParams);
IpuAmmu.cfg : same as the ex02_messageQ example
config.bld :
var evmDRA7XX_ExtMemMapDsp = {
...
SR_0: {
name: evmDRA7XX_SR_0.name,
base: evmDRA7XX_SR_0.base,
len: evmDRA7XX_SR_0.len,
space: "data",
access: "RW"
}
};
Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
externalMemoryMap: [
[ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
[ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
[ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
[ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
[ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
[ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ],
[ evmDRA7XX_SR_0.name, evmDRA7XX_ExtMemMapDsp.SR_0 ]
],
codeMemory: "EXT_CODE",
dataMemory: "EXT_DATA",
stackMemory: "EXT_DATA",
};
var evmDRA7XX_ExtMemMapIpu1 = {
...
SR_0: {
name: evmDRA7XX_SR_0.name,
base: evmDRA7XX_SR_0.base,
len: evmDRA7XX_SR_0.len,
space: "data",
access: "RW"
}
};
Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
externalMemoryMap: [
[ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
[ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
[ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
[ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
[ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
[ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ],
[ evmDRA7XX_SR_0.name, evmDRA7XX_ExtMemMapIpu1.SR_0 ]
],
codeMemory: "EXT_CODE",
dataMemory: "EXT_DATA",
stackMemory: "EXT_DATA",
};
rsc_table_ipu.h :
#define IPU_SR0_VIRT 0xBFB00000
#define IPU_SR0 0xBFB00000
#define IPU_SR0_SIZE (SZ_1M * 1)
struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
...
{
TYPE_DEVMEM,
IPU_SR0_VIRT, IPU_SR0,
IPU_SR0_SIZE, 0, 0, "IPU_SR0",
},
};
rsc_table_dsp.h :
#define DSP_SR0_VIRT 0xBFB00000
#define DSP_SR0 0xBFB00000
#define DSP_SR0_SIZE (SZ_1M * 1)
struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
...
{
TYPE_DEVMEM,
DSP_SR0_VIRT, DSP_SR0,
DSP_SR0_SIZE, 0, 0, "DSP_SR0",
},
};
Configuration :
BIOS: 6.46.01.38
IPC: 3.44.0.0
XDC tools: 3.32.01.22
In the IPU, the GateMP_create() function returns the following error : "ti.sdo.ipc.GateMP: line 1160: assertion failure: A_noHeap: Region has no heap" (What does "createHeap: true" mean ?)
If a create an HeapBufMP (DSP side), and i try to open it (IPU side), the the HeapBufMP_open() function returns : HeapBufMP_E_NOTFOUND.
Do you have any idea why i can not create a GateMP on the IPU core ? And why i try to open an heap, it doesn't find it ?
Thank you for your help,
Olivier
