I am testing multi-word message framing with the McBSP Drivers on the OMAPL1138 Experimenter Board using Digital Loopback. I have been getting very erratic initialization when I use multi word frames. I have modified the mcbspSampleMaster_io.c example in the OMAPL138 BIOSPSP 01.30.01 release. Once successfully initialized the L138 successfully transfers large buffers in 200 word frames. However initialization is quite erratic. It usually takes several tries.
I have inspected the McBSP registers and the initialization problem appears to happen when the McBSP SRGR is not successfully initialized by the drivers. This only becomes a problem when you use multiword frames. I have found the problem to be very repeatable with multi word frames using 12 bit words.
Is this a hardware problem? Is there a workaround for this initialization problem?
OMAPL138 BIOSPSP 01.30.01
DSP/BIOS PSP 1.30.01 MCBSP Drivers with the L138 Experimenter Board
/* \file mcbspSampleMaster_io.c
* \version 0.1
* 100804 DJS Controlled Dynamics Inc.
* Modified for Digital Loop Back to have both Master Transmit and Slave Receive
* 200 12 Bit Words per Frame at a 2000 Hz Frame Rate. A 4.8MHz Clock.
*
*/
#define NUM_BUFS 1 /* Max of 1 outstanding requests */
#define BUFALIGN 128 /* align buffers to 128 bytes */
#define BUFSIZE 16 /* w64 1K of data transceive */
#define LOOP_COUNT 100
#define DEFAULT_BITPERSAMPLE 12 /* number of bits per slot */
#define NUM_OF_CHANNELS 100 /* w200 Number of slots to be used*/
/**< settings to configure the TX or RX hardware sections */
Mcbsp_DataConfig mcbspChanConfig =
{
Mcbsp_Phase_SINGLE,
Mcbsp_WordLength_12,
Mcbsp_WordLength_12, /* Dont care for single phase*/
NUM_OF_CHANNELS,
NUM_OF_CHANNELS, /* Dont care for single phase*/
Mcbsp_FrmSync_DETECT,
Mcbsp_DataDelay_0_BIT,
Mcbsp_Compand_OFF_MSB_FIRST,
Mcbsp_BitReversal_DISABLE,
Mcbsp_IntMode_ON_SYNCERR,
Mcbsp_RxJust_RZF, /* Dont care for TX */
Mcbsp_DxEna_OFF
};
/**< clock setup for the TX section */
Mcbsp_ClkSetup mcbspTXClkConfig =
{
Mcbsp_FsClkMode_INTERNAL, /* Mcbsp_FsClkMode_INTERNAL */
2000, /*2000 2KHz */
Mcbsp_TxRxClkMode_INTERNAL,
Mcbsp_FsPol_ACTIVE_HIGH,
Mcbsp_ClkPol_RISING_EDGE
};
/**< clock setup for the RX section */
Mcbsp_ClkSetup mcbspRXClkConfig =
{
Mcbsp_FsClkMode_EXTERNAL, /* Mcbsp_FsClkMode_INTERNAL */
2000, /* 2000 2KHz */
Mcbsp_TxRxClkMode_EXTERNAL,
Mcbsp_FsPol_ACTIVE_HIGH,
Mcbsp_ClkPol_RISING_EDGE
};
