Other Parts Discussed in Thread: TPS659037
Hello, TI Experts,
Our customer sent us a question about AM5728 Power Down Sequence with PMIC(TPS6590377ZWST).
They found the description of Power Down Sequence from Figure 5-2 of AM5728 Datasheet(SPRS953B).
From this data sheet, SMPS3, LDOLN and LDO2 looks deactivate at different timing (sequentially).
- SMPS3:vdds_ddr2, vdds_ddr1,ddr1_vref0 ,ddr2_vref0
- LDOLN:vdda_abe_per, vdda_ddr, vdda_debug,vdda_dsp_eve, vdda_gmac_core,vdda_gpu,vdda_iva, vdda_video,vdda_mpu, vdda_osc
- LDO2: vdds18V, vdds_mlbp,vdds18v_ddr1,vdds18v_ddr2,vdda_rtc
And they also found the description of Power Down Sequence from Figure 9 of TPS659037 User's Guide(SLIU011D).
From the user guide, SMPS3, LDOLN and LDO2 looks deactivate at the same timing.
Question:
Is it OK to deactivate SMPS3, LDOLN and LDO2 at same timing such as Figure 9 of TPS659037 User's Guide(SLIU011D)?
If it is not OK, please tell us the timing specification (xx[us]) between each signals.
- How much delay([us]) is required from SMPS3 deactivation to LDOLN?
- How much delay([us]) is required from LDOLN deactivation to LDO2?
Best regards,
