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DM642 boot problem

I have a custom board with a DM642 processor. There is a power supervisory chip and watchdog IC on board. When the board is powered up it boots into a bootloader loaded from flash which will after a few seconds delay run the main application. Both the bootloader and the main application periodically reset the watchdog to prevent a reset in normal condition. The main application can reset the board by not servicing the watchdog.

The problem is that when reset is done by the watchdog, the secondary bootloader no longer loads and runs (it runs after power up) and therefore main app will no longer run. Since no application is running the board keeps reseting by the watchdog every 4 seconds (watchdog period). I have monitored the reset line and it is a clean 200ms low signal. If I power cycle the board everything is fine.

What could be difference between a power up reset and a reset signal while power is on?

Any help will be much appreciated.

Farshad

 

  • Is this something that happens every single time, or is this a intermittent failure?

    farco said:
    What could be difference between a power up reset and a reset signal while power is on?

    It has been a long time since I worked with DM642 boot issues, but I believe you should have the same functionality either way, of course there could be system issues that cause such failure, such as if something on the board is inadvertently driving the memory bus that would otherwise get reset with the power cycle.

  •  

    Bernie Thompson said:
    It has been a long time since I worked with DM642 boot issues, but I believe you should have the same functionality either way, of course there could be system issues that cause such failure, such as if something on the board is inadvertently driving the memory bus that would otherwise get reset with the power cycle.
    As Bernie suggests the only reason a power cycle should be different than a reset is if something external to the DSP is acting differently (e.g., something strapped to a boot pin is at a different logic level when the DSP is released from reset). You should be able to watch the DM642 bootloader copy its 1K from Flash after releasing it from reset so I suggest watching the EMIF to see if the device is active.

  • This happens all the time, but I should have mentioned that the firmware is fine since it runs correctly on another batch of boards. As you have suggested it looks like a hardware related issue, I just have to figure out the critical points to check.

  • I suggest looking at Chapter 3 on Device Configurations in the datasheet as this should be a good starting point. I am not sure how easy it will be to capture the state of some of these pins after the watchdog resets the system but if you can do so that may point you in the right direction.

  • I finally got a chance to have look at the board and this problem. It appears that the new DM642 chips that we have used for this production behave differently from the previous ones. It seems that the AEA[20:19] which are used for clock source selection for the EMIF do not have the correct logic levels when a reset signal is applied to the DSP. According to page 34 of the DM642 manual these pins of the DM642 have internal pull down resistors. We have provided a pullup for AEA[20] and relied on the internal pull down resistor to keep AEA[19] at logic level LOW. However it turns out that the internal pull down does not do the work as expected. By connecting a 3k3 ohm resistor from this pin to GND, problem is resolved. It is noted that the same hardware PCB and assembly with previous batch of DM642 chips works fine without the need for this additional external pull down resistor.

    I hope this would be of help to others who may have seen a similar problem.