Can't open /dev/video0

Hi,

If your sensor driver is correctly registered to the vpfe driver, open is failing because /dev entry is not getting created. Try creating /dev entry using mknod command and see if it helps.

Thanks,

Brijesh

/dev entry has already been created :

root@dm365-evm:/opt/examples-davinci/imp-prev-rsz/dm365# ls -l /dev/video0
crw-rw----    1 root     video     81,   0 Jan  1  1970 /dev/video0

So, i guess that the sensor driver is not correctly registered to the vpfe driver...

What should i change ?

I did the following change :

in board-dm365-evm.c :

I add

static struct v4l2_input mt9d131_inputs[] = {
    {
        .index = 0,
        .name = "Camera2",
        .type = V4L2_INPUT_TYPE_CAMERA,
    }
};

and in static struct vpfe_subdev_info vpfe_sub_devs[] :

    {
        .module_name = "mt9d131",
        .is_camera = 1,
        .grp_id = VPFE_SUBDEV_MT9T031,
        .num_inputs = ARRAY_SIZE(mt9d131_inputs),
        .inputs = mt9d131_inputs,
        .ccdc_if_params = {
            .if_type = VPFE_YCBCR_SYNC_8,
            .hdpol = VPFE_PINPOL_POSITIVE,
            .vdpol = VPFE_PINPOL_POSITIVE,
        },
        .board_info = {
            I2C_BOARD_INFO("mt9d131", 0x5d),
            /* this is for PCLK rising edge */
            .platform_data = (void *)1,
        },
    }

and in my bootargs are :

setenv bootargs mem=60M console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=$(nfshost):$(rootpath), ip=192.168.2.199 video=davincifb:vid0=OFF:vid1=OFF:osd0=720x576x16,2025K vpfe_capture.interface=1 vpfe_capture.debug=1

PS : I am a noob

Hi,

I see some messages at the time of boot

dm365evm_enable_pca9543a, status = -121

See if  it is failing because failed status of pca9543. Also see are there mode devices for video in /dev?

Thanks,

Brijesh

The status of the pca9543 means that there is nothing connecting... It could be my problem, but I really don't know what to change... In fact, it should work with a mt9t031... why not with a mt9d131 ?

1- why does pca9543 have to do with the ccdc ?

2 - If YCINSWP is high : I have to use YIN for YUV_8_SYNC, right ?

the ccdc should be configure in ycbcr mode with my settings, but when I print CCDCFG all the bits are low and MODESET is to 0x2000. Strange :/

 In my mode devices, there are video0 to 3, v2l, fb0 to 3 (and i2c-1).

hey guys,

Could anyone help me  ?

The I2C cannot see the sensor... but I really don't know why...

OK, I have been working on integrating a mt9p031 sensor to the git kernel.  I ran into the same problem of the i2c not being read.

I got this working by adding code (included below) at the end of the dm365evm_reset_imager routine in board-dm365-evm.c.  This is the slightly modified reset routine from mt9xxx_set_input_mux from sdk2.10 video_davinci_evm.c.  i2c now reads the imager registers correctly.

Note that this has nothing to do with the "dm365evm_enable_pca9543a, status = -121" error.  I'm still getting that.

Cheers,

-Vim

#include "cpld.h"

    int err = 0;
    u8 valvv[2];
    u32 val1;
    valvv[0] = 8;
    valvv[1] = 0x80;
   
    /* Drive TVP5146 Reset to low */
    //tvp514x_hw_reset(0);
   
    val1 = __raw_readb(cpld + DM365_CPLD_REGISTER19);
    val1 |= 0x01010101;
    __raw_writeb(val1, cpld + DM365_CPLD_REGISTER19);
   
    /* drive the sensor reset line high */
    //image_sensor_hw_reset(1);
    // enable CCD power Vout4
    val1 = __raw_readb(cpld + DM365_CPLD_REGISTER5);
    val1 |= DM365_CCD_POWER_MASK;
    __raw_writeb(val1, cpld + DM365_CPLD_REGISTER5);
   
    val1 = __raw_readb(cpld + DM365_CPLD_REGISTER3);
    val1 |= DM365_IMAGER_RST_MASK;
    __raw_writeb(val1, cpld + DM365_CPLD_REGISTER3);
    /* CPLD to Route GPIO to Imager Reset line */
    val1 = __raw_readb(cpld + DM365_CPLD_REGISTER16);
    val1 &= ~0x40404040;
    __raw_writeb(val1, cpld + DM365_CPLD_REGISTER16);
    val1 = __raw_readb(cpld + DM365_CPLD_REGISTER18);
    val1 |= 0x20202020;
    __raw_writeb(val1, cpld + DM365_CPLD_REGISTER18);
    val1 = __raw_readb(cpld + DM365_CPLD_REGISTER18);
    val1 &= ~0x01010101;
    __raw_writeb(val1, cpld + DM365_CPLD_REGISTER18);
    /* Pin mux to use GPIO40 */
    //    davinci_cfg_reg(DM365_GPIO40, PINMUX_RESV);
   
    davinci_cfg_reg(DM365_GPIO40);
    gpio_request(40, "sensor_reset");
   
    /* Configure GPIO40 to be output and hight */
    gpio_direction_output(40, 1);
   
    /* Set Mux for image sensor */
    val1 = __raw_readb(cpld + DM365_CPLD_REGISTER3);
    val1 &= ~DM365_VIDEO_MUX_MASK;
    val1 |= DM365_SENSOR_SEL;
    __raw_writeb(val1, cpld + DM365_CPLD_REGISTER3);