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TMS320C6748: SPI and PWM

Roberto Zanaboni1
Prodigy 220 points
Part Number: TMS320C6748
Other Parts Discussed in Thread: TLV320AIC3106

Dear forum

I need to use SPI for control a device; this device, as tipical, have the SS input pin.

Question are:

1)Connect to SS, i need to use the SPI0_ENA or the SPI0_CS[0] of the C6748 ?

2) In case SPI0_ENA is not necessary, can I use it as EPWM0B ...the PWM genrator ? 

3)The PWM will generate a square wave 50% as input clock for a Audio Codec. It is good for this purpose

    or the square quality is low for such application ?

Many Thanks

Roberto

  • 0
    TI__Guru**** 161600 points
    Hi Roberto,

    1). This depends on your use case. See the SPI operation modes, Section 28.2.3 Operation Modes from TMS320C6748 TRM:
    "The 3-pin option is the basic clock, data in, and data out SPI interface and uses the SPIx_CLK, SPIx_SIMO, and SPIx_SOMI pins. The 4-pin with chip select option adds the SPIx_SCS[n] pin that is used to support multiple SPI slave devices on a single SPI bus. The 4-pin with enable option adds the SPIx_ENA pin that is used to increase the overall throughput by adding hardware handshaking. The 5-pin option uses all the SPI pins and is a superset of the different options."

    If you have only one slave on the SPI bus, in my opinion you can use the 3-pin mode (no SPI_CS or SPI_ENA). If you use multiple slaves on the bus, you need to use SPI_CS. If you target a throughput, you should use SPI_ENA.

    2) Yes, this should be possible.

    3). It is possible, if you can achieve the required clock frequency, but I wouldn't use the PWM as a clock for audio codec. You have a dedicated audio interfaces: McASP and McBSP.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 220 points

    Thanks for reply Mr Yordan

    you was very clear.

    About the Audio Codec : this need a input clock named MCLK (as in the famous Codec TLV320AIC3106 of the C6748 LCD DEV KIT)  in a range beetwen 10M and 60MHZ.

    I belive the McBSP and McABSP are not able to produce this clock..This ports generate the CLKXi clock for the Codec input BCLK (Bit CLK in I2S) ,but not the MCLK (Master CLK).

    Is true or Im missing some ?

    So I would like to use the PWM for MCLK

    Thanks for your time

    Roberto

  • 0 in reply to Roberto Zanaboni1
    TI__Guru**** 161600 points
    Hi,

    See Table 6-57. Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V](1) (see Figure 6-34).
    If you use ASYNC3 in 1.1V NOM, then you will get ASYNC3 to 100MHz => MCBSP CLKR/X Cycle time will be 20ns, which gives you 50MHz.
    Another approach is to use external clock.

    I am also looping the hw experts to elaborate if there is a better option.

    Best Regards,
    Yordan
  • 0 in reply to Roberto Zanaboni1
    TI__Mastermind 43660 points
    Roberto,

    In case of McASP, you have AHCLKR/X which is receive/transmit master clock. You can generate this either internal or source through external clock. You can also refer below clocking tool for McASP and McBSP.

    processors.wiki.ti.com/.../AM18xx

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 220 points

    Thanks very much for lot of information

    Roberto