66AK2G02: Question for DDR3 schematic review

Hi,

Although I informed we confirmed working with DDR3L only and we have not verified with DDR3, customer will use DDR3, and I think DDR3 also should work, right?

You must follow the Data Manual recommendations. That being said you can see that DM talks about connecting DDR3L NOT DDR3, so you should advise your customer to use DDR3L.

* When 1 x 16bit DDR3 used, should DQS2,3 be pull-up and down, right?

See Section 7.1.2.3.2 16-Bit DDR3L Interface:
"When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off the DDR3_DQS*_Pi pins to ground via a 1k-Ω resistor and to tie off the DDR3_DQS*_Ni pins to the corresponding DVDD_DDR supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection against external electrical noise causing activity on the signals."

* When I checked GP EVM and ICE board, RZQ pin was pull-down using 240Ohm, but I found below comments on datasheet and pull-down resister value is different. Could you please let me know what is correct?

You must follow the Data Manual in cases when reference designs differ from DM recommendations.

When DDR_PLL should be implemented?

DDR_PLL: (EMIF / DDR PHY) The DDR PLL is used to drive the DDR3 PHY for the EMIF
See also Section 5.9.3.3.1 DDR_PLL Settings of the Data Manual.

* Could you please check below my customer's terminator implementation? DDR_REF_0.75V_PW can be used for VDDR_VTT, right?

See Section 7.1.2.13 VTT. VTT needs to be half the DDR3L supply voltage. The termination seems fine.

I am also looping the hw experts to elaborate if necessary.

Best Regards,
Yordan

Hi,

Let me add some additional comments. 

* When I checked GP EVM and ICE board, RZQ pin was pull-down using 240Ohm, but I found below comments on datasheet and pull-down resister value is different. Could you please let me know what is correct?

In Table4-3 of datasheet, 

(1) An external 49.9Ω ±1% resistor must be connected between this pin and VSS

This is an error in the data manual. The value of the resistor should be 240 ohms as implemented on the EVMs.

* DDR3_CLKOUT_P0/N0 should be connected to CK pin of DDR3 memory?

The DDR3_CLKOUT_P0/N0 must be connected to the DDR3 memory and must be connected with the P0 signal connected to the P clock input and the N0 connected to the N clock input. 

* DDR_CLK_P/N should be opened when DDR_PLL was not used?

The DDR_PLL must always be programmed if the DDR3 interface is used but he DDR_PLL can be sourced from either the SYSCLK of the DDR_CLK_P/N pins. If the DDR_PLL is sourced from SYSCLK, the DDR_CLK_P/N can be left unconnected. 

*When DDR_PLL should be implemented?

The DDR_PLL must always be programmed if the DDR3 interface is used

* Can DDR_RESET be connected to DDR3 memory without pull-down? I found DDR_RESET was pull-down in ICE board schematic.

The pull down is present to ensure that the part remains in reset until the K2G is initialized and ready to operate the DDR. I recommend that you include that resistor. 

* Could you please check below my customer's terminator implementation? DDR_REF_0.75V_PW can be used for VDDR_VTT, right?

The schematic is a little difficult to read but it appears that DDR_REF_0.75V_PW is created using a voltage divider. This does not meet the requirements for VTT as specified by IEEE. The VTT termination voltage must be supplied by a push/pull power supply output. The LP2996A used on the EVMs is specifically designed to provide a VTT termination voltage for DDR3L components. 

Regards,

Bill