DRA622C-Q1: Ethernet in RMII mode - 50MHz reference clock

It seems there is no RMIIx_IO_CLK_EN in GMII_SEL for J5Eco. Only possibility is to set REFCLK_SOURCE bit in RMII_REFCLK_SRC register.

Andrzej,

Did you check if it is clock collision by using a scope?

It will save you time and you would be able to proceed with the debug.

Moreover, I have the feeling you are getting different symptoms than those in the thread you are referring to/

Best Regards,

Stan

Andrzej Polanski16 said:

There is misleading information in J5Eco TRM:
"4.2.2 Ethernet Switch RMII Clocking Details
...
The operation is controlled by the GMII_SEL[RMIIx_IO_CLK_EN] fields in the Control Module..."

but there is no RMIIx_IO_CLK_EN in GMII_SEL register...
see "3.2.33 GMII_SEL Register (offset = 650h) [reset = 0h]"

This seems to be TRM error. You can submit TRM update from the "Submit Documentation Feedback" button.

Andrzej Polanski16 said:

only way to disable internal clock is via "REFCLK_SOURCE bit in RMII_REFCLK_SRC register" (as I have already posted).

Yes, this is described in TRM section 2.3.5 (as I have already posted). Do you expect this internal clock selection to be available from two places (two registers)? If yes, why?  RMII_REFCLK_SRC[0] REFCLK_SOURCE bit should be enough. Why you need one more register to do this?

Regards,
Pavel

Andrzej,

Did you check with a oscilloscope if it is the clock collision issue in the thread you have seen?

If not, you will not need to disable J5's clock, or one way or another will give you a clue.

Regards,

Stan