Linux/DRA722: jitter happen when the pixelclock is too big

samgyung zhang

Part Number: DRA722

Tool/software: Linux

Hi,I met a problem.I am using a display screen that its' resolution is 1920*720@60.From the screen's datasheet,it indicated that i should confige the pixelclock to 88Mhz .But after i do that ,i found jitter happened continuously on the screen.If i change its pixelclock to 75Mhz,everything seem ok.My lcd is using DPLL_VIDEO1 as its source clock.I have found some ideas in E2E forum.Someone thought that DPLL_HDMI is good at improving the issue like that.As you can checkout in the following link:

Can you tell me that if the DPLL_VIDEO1 cannot support the resolution like that 1920*720@60?Or can you give me some indicate that how to change to DPLL_HDMI?I am using GLSDK 7_00_00_04 ,kernel 3.14

Thank you very much！

over 9 years ago

0 Mariya Petkova over 9 years ago

TI__Expert 4885 points

Hi, samgyung zhang,

DSS expert is notified about your query and will respond here.

Regards,
Mariya

0 Venkat Mandela over 9 years ago in reply to Mariya Petkova

TI__Expert 5980 points

Hi,

Can you attach a screen shot of your LCD in the working and non working scenarios? Also please share register dumps in both cases using
git.ti.com/.../dss_clockdumps.sh

1920x720 should be within the resolutions supported by VOUT1. I will confirm this.

The link you posted is specifically related to display connections over FPDLink. Are you using FPDLink to connect to a LCD?

Switching VOUT clock to use HDMI PLL cannot be done cleanly in K3.14. If you can use K4.4, it is a one line change.

regards,
Venkat

0 samgyung zhang over 9 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,Venkat Mandela

Thanks for your respond,the phenomenon of the issue is that sometimes there is a flicker on the sceen,especially when i change the gfx layer to the vid3 layer.On the other hand,it would product some error like the following:

[ 57.016143] [drm:omap_plane_error_irq] *ERROR* vid3: errors: 00100000

[ 57.022635] [drm:omap_crtc_error_irq] *ERROR* lcd: errors: 00004000

[ 57.028929] [drm:omap_plane_error_irq] *ERROR* gfx: errors: 00000040

[ 57.035366] [drm:omap_plane_error_irq] *ERROR* vid3: errors: 00100000

[ 57.041835] [drm:omap_plane_error_irq] *ERROR* gfx: errors: 00000040

[ 57.050004] dmm 4e000000.dmm: sDMA write transfer timeout

something must be pointed out is that the errors abot only occur when I change the gfx layer to vid3 layer,as the vid3 layer is used for reversing video!In other case ,it do not product that kind of errors,but sometimes there is a flicker on the sceen

I have tested the dss_clockdumps.sh ,you can compare the 75Mhz_dumps.txt and 88Mhz_dumps.txt in the attachment.

Fullscreen 75Mhz_dumps.txt Download

16282.93> =====================DSS clock script===================
16282.93> Dumps internal clocks and muxes of DSS
16282.93> 
16283.01> CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A6
16283.02> video1 PLL :  Enabled
16283.02> video2 PLL :  Disabled
16283.02> HDMI   PLL :  Disabled
16283.02> DSI1_A_CLK mux : DPLL Video1
16283.02> DSI1_B_CLK mux : DPLL video2
16283.02> DSI1_C_CLK mux : DPLL Video2
16283.02> 
16283.02> DSS_CTRL (0x58000040) = 0x00010001
16283.02>  2: LCD1 clk switch :  DSI1_A_CLK
16283.02>  3: LCD2 clk switch :  DSS clk
16283.02> 10: LCD3 clk switch :  DSS clk
16283.02>  1: func clk switch :  DSS clk
16283.02> 13: DPI1 output     :  LCD1
16283.04> 
16283.08> ========================================================
16283.08> Register dump for DPLL video1
16283.08> |----------------------------|
16283.08> | Address (hex) | Data (hex) |
16283.08> |----------------------------|
16283.10> | 0x58004300    | 0x00000018 |
16283.10> | 0x58004304    | 0x00002283 |
16283.10> | 0x58004308    | 0x00000000 |
16283.10> | 0x5800430C    | 0x00601E00 |
16283.10> | 0x58004310    | 0x00616008 |
16283.10> | 0x58004314    | 0x00000000 |
16283.10> | 0x58004318    | 0x00000000 |
16283.10> | 0x5800431C    | 0x00000000 |
16283.10> | 0x58004320    | 0x00000000 |
16283.10> |----------------------------|
16283.10> 
16283.10> Details for DPLL video1
16283.10> PLL status  :  Locked
16283.10> M4 hsdiv(1) :  Active
16283.12> M5 hsdiv(2) :  inactive
16283.12> M6 hsdiv(3) :  inactive
16283.12> M7 hsdiv(4) :  inactive
16283.12> 
16283.12> PLL_REGM =  15
16283.12> PLL_REGN =  0
16283.18> M4 DIV   =  3
16283.19> M6 DIV   =  0
16283.19> M7 DIV   =  0
16283.19> 
16283.19> Clock calculations (DPLL video1)
16283.19> sysclk = 20000000
16283.19> DCO clk = sysclk * 2 * REGM / (REGN + 1) = 600000000
16283.19> M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 150000000
16283.19> M6clk (clkcout1) = DCO clk / (M6 DIV + 1) = 0
16283.21> M7clk (clkcout1) = DCO clk / (M7 DIV + 1) = 0
16283.21> 
16283.21> ========================================================
16283.21> Clock O/P of MUXes
16283.21> Error: I2C Read failed
16283.21> Error: I2C Read failed
16283.21> Error: I2C Read failed
16283.21> omapconf: powerdm_deinit(): cpu not supported!!!
16283.21> omapconf: clockdm_deinit(): cpu not supported!!!
16283.21> DSI1_A_CLK :  150000000
16283.21> DSI1_B_CLK :  0
16283.21> DSI1_C_CLK :  0
16283.21> 
16283.22>  2: LCD1 clk :  150000000
16283.24>  3: LCD2 clk :  192000000
16283.24> 10: LCD3 clk :  192000000
16283.24>  1: func clk :  192000000
16283.24> 
16283.32> LCD1 logic clk(/ 1 ) :  150000000  pix clk(/ 2 ) :  75000000
16283.32> LCD2 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000
16283.33> LCD3 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000

Fullscreen 88Mhz_dumps.txt Download

  453.90> 
  453.91> =====================DSS clock script===================
  453.91> Dumps internal clocks and muxes of DSS
  453.91> 
  453.97> CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A6
  453.99> video1 PLL :  Enabled
  453.99> video2 PLL :  Disabled
  453.99> HDMI   PLL :  Disabled
  453.99> DSI1_A_CLK mux : DPLL Video1
  453.99> DSI1_B_CLK mux : DPLL video2
  453.99> DSI1_C_CLK mux : DPLL Video2
  453.99> 
  453.99> DSS_CTRL (0x58000040) = 0x00010001
  453.99>  2: LCD1 clk switch :  DSI1_A_CLK
  453.99>  3: LCD2 clk switch :  DSS clk
  454.00> 10: LCD3 clk switch :  DSS clk
  454.00>  1: func clk switch :  DSS clk
  454.00> 13: DPI1 output     :  LCD1
  454.00> 
  454.05> ========================================================
  454.05> Register dump for DPLL video1
  454.07> |----------------------------|
  454.07> | Address (hex) | Data (hex) |
  454.07> |----------------------------|
  454.07> | 0x58004300    | 0x00000018 |
  454.07> | 0x58004304    | 0x00002283 |
  454.07> | 0x58004308    | 0x00000000 |
  454.07> | 0x5800430C    | 0x00801600 |
  454.07> | 0x58004310    | 0x00616008 |
  454.07> | 0x58004314    | 0x00000000 |
  454.07> | 0x58004318    | 0x00000000 |
  454.07> | 0x5800431C    | 0x00000000 |
  454.07> | 0x58004320    | 0x00000000 |
  454.07> |----------------------------|
  454.08> 
  454.08> Details for DPLL video1
  454.08> PLL status  :  Locked
  454.08> M4 hsdiv(1) :  Active
  454.08> M5 hsdiv(2) :  inactive
  454.08> M6 hsdiv(3) :  inactive
  454.08> M7 hsdiv(4) :  inactive
  454.08> 
  454.16> PLL_REGM =  11
  454.16> PLL_REGN =  0
  454.18> M4 DIV   =  4
  454.18> M6 DIV   =  0
  454.18> M7 DIV   =  0
  454.18> 
  454.18> Clock calculations (DPLL video1)
  454.18> sysclk = 20000000
  454.18> DCO clk = sysclk * 2 * REGM / (REGN + 1) = 440000000
  454.18> M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 88000000
  454.18> M6clk (clkcout1) = DCO clk / (M6 DIV + 1) = 0
  454.18> M7clk (clkcout1) = DCO clk / (M7 DIV + 1) = 0
  454.18> 
  454.18> ========================================================
  454.18> Clock O/P of MUXes
  454.18> Error: I2C Read failed
  454.18> Error: I2C Read failed
  454.19> Error: I2C Read failed
  454.19> omapconf: powerdm_deinit(): cpu not supported!!!
  454.19> omapconf: clockdm_deinit(): cpu not supported!!!
  454.19> DSI1_A_CLK :  88000000
  454.19> DSI1_B_CLK :  0
  454.19> DSI1_C_CLK :  0
  454.19> 
  454.21>  2: LCD1 clk :  88000000
  454.21>  3: LCD2 clk :  192000000
  454.21> 10: LCD3 clk :  192000000
  454.21>  1: func clk :  192000000
  454.21> 
  454.29> LCD1 logic clk(/ 1 ) :  88000000  pix clk(/ 1 ) :  88000000
  454.30> LCD2 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000
  454.30> LCD3 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000

I am not using the FPDLink to connect to LCD.I am using LVDS with maxim's chip.

That is all,hope you respond me soon!Thank you very much!

0 Venkat Mandela over 9 years ago in reply to samgyung zhang

TI__Expert 5980 points

Hi,

The error bits shown above are buffer underflow bits that indicate that DSS is unable to fetch data fast enough. This is most likely unrelated to the PLL configuration. Can you please explain what are the major data transfers happening in the system when the issue occurs? e.g. camera capture (resolution, format, fps), Display (number of layers used, fps, resolution, format)?

Can you please clarify what you mean by "when i change the gfx layer to the vid3 layer" ? Are you referring to the layer displayed on the top?

regards,
Venkat

0 samgyung zhang over 9 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,Venkat,

Please fogive my bad desciption ,As you know,dra722 have four pipelines,one graphics pipeline (GFX), three video pipelines(vid3,vid2,vid1),From the top to bottom,its zorder like that "GFX→vid3→vid2→vid1.the GFX is the top layer,used for displaying GUI.The vid3 is used for displaying logo,the logo is a ppm picture and its' size is 1920*720*32bit,vid1 is used for reserving video,it is BT655 format and its' resolution is 1920*720@50,I have try to reduce the FPS of the video,but it did't work.It seem that there are some problems in lcd output while switching to different pipelines.Is that the data transfer is too big?

Thans for your reading!

0 Venkat Mandela over 9 years ago in reply to samgyung zhang

TI__Expert 5980 points

Hi,

Sorry for the delay in response. I was on leave for the last two weeks.

I will check if I can reproduce the issue on DRA72x EVM with 1920x1200 OSD panel. Please confirm the assumptions when the issue occurs.

1. VID3 is used for displaying logo. This a full screen image.
2. GFX is used for UI layer. (size ?)
3. VID1 is used to display captured video (BT655 format 1920x720@50 fps)
4. VID3 is the bottom layer
5. GFX is the middle layer
6. VID1 is the top layer

regards,
Venkat

0 samgyung zhang over 9 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,venkat:

Sorry for too late to respond you,I was on leave for the last week too.

1. VID3 is used for displaying logo. This a full screen image.                   -------------Its' sizeis 1920*720*32,as it is a ARGB picture.
2. GFX is used for UI layer. (size ?)                                   ---------its' size is 1920*720*24
3. VID1 is used to display captured video (BT655 format 1920x720@50 fps)
4. VID3 is the bottom layer                          ---------VID3 is the layer only below the GFX layer,From the top to bottom,its zorder like that "GFX→vid3→vid2→vid1
5. GFX is the middle layer
6. VID1 is the top layer

Thanks for reading!Hope to get your advise soon!

0 Venkat Mandela over 9 years ago in reply to samgyung zhang

TI__Expert 5980 points

Hi,

I have tried overlaying 4 planes onto the 1920x1200 LCD we have but did not run into the issue. Perhaps it has something to do with the concurrent capture. I will test further and get back to you.

regards,
Venkat

0 samgyung zhang over 9 years ago in reply to Venkat Mandela

Expert 1060 points

HI,

THanks for respond.

In fact,the vid3,vid2,vid1 pipeline are used simultaneously!

0 samgyung zhang over 9 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,Venkat Mandela :
Have you tested the 4 pipelines onto the 1920x1200 simultaneously?Is that run well?

0 Venkat Mandela over 9 years ago in reply to samgyung zhang

TI__Expert 5980 points

Hi,

I have tested 4 pipelines on DRA722 using kmstest example application. This is part of Processor SDK - Linux Automotive 3.x release filesystem.

kmstest -c 0 -p 1920x1200 -p 1920x1200 -p 1920x1200 -r 1920x1200

This is simply overlaying four planes on top of one another. kmstest provides options to specify the frame buffer dimensions and format and positioning. Can you try testing your plane overlay order/format with kmstest? You can try using "kmstest --help" for command line usage.

if you are on a older release, you can cross-compile the tool from the below links.

github.com/.../
processors.wiki.ti.com/.../Processor_SDK_Linux_Automotive_Application_Notes

regards,
Venkat

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Linux/DRA722: jitter happen when the pixelclock is too big