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AM3352: GPMC timing questions

Kummi
Mastermind 6220 points
Part Number: AM3352

Hi,

We are using AM3352 GPMC to access FPGA(Synchronous) and need some clarification on
the GPMC chip select tw(csnV) timings.

1.We couldn't understand why Synchronous Multiple (Burst) Read (Figure 7-20) has
CSRDOFFTIME is divided into two (CSRDOFFTIME0 and CSRDOFFTIME1)
whereas Synchronous Multiple (Burst) write(Figure 7-22) has one CSWROFFTIME?

Synchronous Multiple (Burst) Read:

Synchronous Multiple (Burst) write:

2.As per the the Datasheet "Table 7-22" the chip select pulse duration tw(csnV) is
calculated with the below equation.
A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK

With the above equation the burst time is calculated with the difference of
CSOffTime and CSOnTime and we believe it will be a big value.
In case of actual design do we need to follow both datasheet calculation and
the TRM manual(Figure 7-20/Figure 7-22) as well?

Best Regards
Kummi

  • 0
    TI__Guru**** 393215 points
    Hi,

    1. The read timing is shown in this way to emphasize the fact that there are different burst sizes supported.
    2. Note that here the internal GPMC_FCLK is used in the calculation, not the external GPMC_CLK. Also CSRdOffTime here is equal to the CSRDOFFTIME0 from the TRM, and PageBurstAccessTime is equal to CSRDOFFTIME1.
  • 0
    Mastermind 6220 points

    Part Number: AM3352

    Hi,

    With regards to the AM335x GPMC Wait Setup/Hold time.

    Synchronous Burst Write(Figure 7-21) timing mentions that Hold time(F22) is the
    hold time when WAIT is HIGH before asserting the WAIT and SetUp time(F21) is the
    setup time when WAIT is HIGH after asserting the WAIT.As shown below.

    F21-> Setup time, input wait gpmc_wait[x] valid before output clock gpmc_clk high
    F22-> Hold time, input wait gpmc_wait[x] valid after output clock gpmc_clk high



    But in general we believe the concept of Setup and Hold time is opposite.
    As mentioned in case of Synchronous Burst Read(Figure 7-18) below.




    Question:
    In case if we want to use Wait during Write access, is it necessary that WAIT should
    be HIGH before deasserting the WAIT?

    Best Regards
    Kummi

  • 0 in reply to Kummi
    TI__Guru**** 393215 points
    If by deasserting you mean transition from high to low, then yes.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 6220 points
    Hi Biser,

    Thank you for the answer,

    deasserting I meant about WAIT disable.

    I am little bit confused about the Synchronous Burst Write(Figure 7-21),
    The setup and Hold time seems opposite. Hold time should be after Setup?

    Best Regards
    Kummi
  • 0 in reply to Kummi
    TI__Guru**** 393215 points
    I have asked the factory team to clarify. They will post here.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 6220 points

    Hi Biser,

    Thank you.

    With regards to the first question about the chip select tw(csnV) timings.

    The CsWrOffTime (Synchronous Multiple write Figure 7-22) seems to be
    longer than CsRdOffTime Synchronous Multiple Read Figure 7-20).Above figures.

    CSRdOffTime (Read) doesn't include PageBurstAccessTime whereas CsWrOffTime(write)
    does include PageBurstAccessTime.

    So is it true that CsWrOffTime is much longer when compared to CSRdOffTime?
    Do we have any reference use case in case of  Synchronous Multiple(Burst) write?
    couldn't find in TRM 7.1.4 Use Cases.

    Best Regards
    Kummi

  • 0 in reply to Kummi
    TI__Guru**** 393215 points
    The TRM figures are for illustrative purposes only. For timing calculations please use the datasheet information.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 6220 points

    Hi Biser,

    Thank you.

    One clarification on this.
    As a conclusion, when calculating  chip select tw(csnV) timings for burst read/write,
    Burst Read or Write both includes "PageBurstAccessTime" as per the equation?



    The Synchronous Multiple (Burst) Read(Figure 7-20) from the TRM showing
    no "PageBurstAccessTime" for CSRdOffTime0 could be a mistake in the TRM?



    I am sorry to bother you, this information is needed for our customers design.

    Best Regards.
    Kummi

  • 0 in reply to Kummi
    TI__Guru**** 393215 points
    Yes, this is correct.
  • 0 in reply to Biser Gatchev-XID
    Mastermind 6220 points


    Hi Biser,

    Thank you.

    Please let me know if there is any updates from the factory team
    about my question regarding the Setup and Hold time mentioned above.
    About Synchronous Burst Write(Figure 7-21),Setup and Hold time in the opposite order.

    Best Regards
    Kummi

  • 0 in reply to Kummi
    TI__Guru* 86820 points

    Kummi, it looks like there is a error in Figure 7-18.  F21 is indeed the setup time of valid wait before CLK high transition.  F22 is the hold time for valid wait after CLK high transition. 

    In the diagram, the WAIT polarity is assumed active low, which means a low level on the WAIT signal indicates that data is not ready.  This may be a bit confusing when looking at setup and hold timing.  The setup time defines the time before CLK high transition that is required to indicate that data is valid.  Similarly, the hold time defines the time after CLK high transition that is required to indicate valid data.

    I will get Figure 7-18 fixed in the next datasheet version.

    Regards,

    James

  • 0 in reply to JJD
    Mastermind 6220 points

    Hi James,

    Thank you for the information.

    I am sorry that we are confused with your comment, we thought there
    is an error in Figure 7-21, but you have mentioned the error in Figure 7-18.
    Could you please reconfirm this.

    As written in my post earlier, Figure 7-21 shows Hold time first and
    Setup time later which is in the reverse order of the concept of Setup and Hold time.

    F22: Hold time, F21: Setup time


    Best Regards
    Kummi

  • 0 in reply to Kummi
    TI__Guru* 86820 points
    Kummi, i agree it is a little confusing, but it is Fig 7-18 that is in error.

    Figure 7-21 is correct. F22 is hold time, which means GPMC_WAIT has to stay high for F22 time in order for the data to be considered valid on that clock edge. Conversely, F21 is the setup time. In other words, GPMC_WAIT has to be high for F21 time before rising edge of the clock in order for the data to be considered valid on that clock edge.

    Regards,
    James